Changeset 0c2d9bb in mainline for kernel/arch


Ignore:
Timestamp:
2013-12-25T22:54:29Z (12 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
b51cf2c
Parents:
f7a33de (diff), ac36aed (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

merge mainline changes

Location:
kernel/arch
Files:
35 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4040
     41#define FRAME_LOWPRIO  0
     42
    4143#include <typedefs.h>
    4244

  • kernel/arch/abs32le/include/arch/mm/page.h

    rf7a33de r0c2d9bb  
    5757
    5858/* Page table sizes for each level. */
    59 #define PTL0_SIZE_ARCH  ONE_FRAME
    60 #define PTL1_SIZE_ARCH  0
    61 #define PTL2_SIZE_ARCH  0
    62 #define PTL3_SIZE_ARCH  ONE_FRAME
     59#define PTL0_FRAMES_ARCH  1
     60#define PTL1_FRAMES_ARCH  1
     61#define PTL2_FRAMES_ARCH  1
     62#define PTL3_FRAMES_ARCH  1
    6363
    6464/* Macros calculating indices for each level. */

  • kernel/arch/amd64/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4040
     41#define FRAME_LOWPRIO  0x1000
     42
    4143#ifndef __ASM__
    4244

  • kernel/arch/amd64/include/arch/mm/page.h

    rf7a33de r0c2d9bb  
    6161
    6262/* Page table sizes for each level. */
    63 #define PTL0_SIZE_ARCH  ONE_FRAME
    64 #define PTL1_SIZE_ARCH  ONE_FRAME
    65 #define PTL2_SIZE_ARCH  ONE_FRAME
    66 #define PTL3_SIZE_ARCH  ONE_FRAME
     63#define PTL0_FRAMES_ARCH  1
     64#define PTL1_FRAMES_ARCH  1
     65#define PTL2_FRAMES_ARCH  1
     66#define PTL3_FRAMES_ARCH  1
    6767
    6868/* Macros calculating indices into page tables in each level. */

  • kernel/arch/amd64/src/ddi/ddi.c

    rf7a33de r0c2d9bb  
    6868                 */
    6969               
    70                 void *store = malloc(bitmap_size(elements, 0), FRAME_ATOMIC);
     70                void *store = malloc(bitmap_size(elements), FRAME_ATOMIC);
    7171                if (!store)
    7272                        return ENOMEM;
    7373               
    7474                bitmap_t oldiomap;
    75                 bitmap_initialize(&oldiomap, task->arch.iomap.elements, 0,
     75                bitmap_initialize(&oldiomap, task->arch.iomap.elements,
    7676                    task->arch.iomap.bits);
    7777               
    78                 bitmap_initialize(&task->arch.iomap, elements, 0, store);
     78                bitmap_initialize(&task->arch.iomap, elements, store);
    7979               
    8080                /*
    … …  
    129129               
    130130                bitmap_t iomap;
    131                 bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, 0,
     131                bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
    132132                    CPU->arch.tss->iomap);
    133133                bitmap_copy(&iomap, &TASK->arch.iomap, elements);
    … …  
    157157       
    158158        descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
    159         size_t size = bitmap_size(elements, 0);
     159        size_t size = bitmap_size(elements);
    160160        gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
    161161        gdtr_load(&cpugdtr);

  • kernel/arch/amd64/src/proc/task.c

    rf7a33de r0c2d9bb  
    4646{
    4747        task->arch.iomapver = 0;
    48         bitmap_initialize(&task->arch.iomap, 0, 0, NULL);
     48        bitmap_initialize(&task->arch.iomap, 0, NULL);
    4949}
    5050

  • kernel/arch/arm32/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_WIDTH  12  /* 4KB frames */
    4040#define FRAME_SIZE   (1 << FRAME_WIDTH)
     41
     42#define FRAME_LOWPRIO  0
    4143
    4244#ifndef __ASM__

  • kernel/arch/arm32/include/arch/mm/page.h

    rf7a33de r0c2d9bb  
    7373
    7474/* Page table sizes for each level. */
    75 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    76 #define PTL1_SIZE_ARCH          0
    77 #define PTL2_SIZE_ARCH          0
    78 #define PTL3_SIZE_ARCH          ONE_FRAME
     75#define PTL0_FRAMES_ARCH  4
     76#define PTL1_FRAMES_ARCH  1
     77#define PTL2_FRAMES_ARCH  1
     78#define PTL3_FRAMES_ARCH  1
    7979
    8080/* Macros calculating indices into page tables for each level. */

  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    rf7a33de r0c2d9bb  
    4848        (((pte_t *) (pte))->l0.descriptor_type != 0)
    4949#define PTE_GET_FRAME_ARCH(pte) \
    50         (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
     50        (((uintptr_t) ((pte_t *) (pte))->l1.frame_base_addr) << FRAME_WIDTH)
    5151#define PTE_WRITABLE_ARCH(pte) \
    5252        (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)

  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    rf7a33de r0c2d9bb  
    4848        (((pte_t *) (pte))->l0.descriptor_type != 0)
    4949#define PTE_GET_FRAME_ARCH(pte) \
    50         (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
     50        (((uintptr_t) ((pte_t *) (pte))->l1.frame_base_addr) << FRAME_WIDTH)
    5151#define PTE_WRITABLE_ARCH(pte) \
    5252        (((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO)

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    rf7a33de r0c2d9bb  
    6060
    6161static struct beagleboard {
    62         amdm37x_irc_regs_t *irc_addr;
     62        omap_irc_regs_t *irc_addr;
    6363        omap_uart_t uart;
    6464        amdm37x_gpt_t timer;
    … …  
    103103            PAGE_NOT_CACHEABLE);
    104104        ASSERT(beagleboard.irc_addr);
    105         amdm37x_irc_init(beagleboard.irc_addr);
     105        omap_irc_init(beagleboard.irc_addr);
    106106
    107107        /* Initialize timer. Use timer1, because it is in WKUP power domain
    … …  
    123123
    124124        /* Enable timer interrupt */
    125         amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
     125        omap_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
    126126
    127127        /* Start timer here */
    … …  
    147147static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate)
    148148{
    149         const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
     149        const unsigned inum = omap_irc_inum_get(beagleboard.irc_addr);
    150150
    151151        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    161161        /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
    162162         * of ISR. DO this to avoid strange behavior. */
    163         amdm37x_irc_irq_ack(beagleboard.irc_addr);
     163        omap_irc_irq_ack(beagleboard.irc_addr);
    164164}
    165165
    … …  
    188188                indev_t *srln = srln_wire(srln_instance, sink);
    189189                omap_uart_input_wire(&beagleboard.uart, srln);
    190                 amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
     190                omap_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
    191191        }
    192192#endif

  • kernel/arch/arm32/src/mach/beaglebone/beaglebone.c

    rf7a33de r0c2d9bb  
    6363
    6464static struct beaglebone {
    65         am335x_irc_regs_t *irc_addr;
     65        omap_irc_regs_t *irc_addr;
    6666        am335x_cm_per_regs_t *cm_per_addr;
    6767        am335x_cm_dpll_regs_t *cm_dpll_addr;
    … …  
    104104
    105105        /* Initialize the interrupt controller */
    106         am335x_irc_init(bbone.irc_addr);
     106        omap_irc_init(bbone.irc_addr);
    107107}
    108108
    … …  
    153153        }
    154154        /* Enable the interrupt */
    155         am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
     155        omap_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
    156156        /* Start the timer */
    157157        am335x_timer_start(&bbone.timer);
    … …  
    176176static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
    177177{
    178         const unsigned inum = am335x_irc_inum_get(bbone.irc_addr);
     178        const unsigned inum = omap_irc_inum_get(bbone.irc_addr);
    179179
    180180        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    187187        }
    188188
    189         am335x_irc_irq_ack(bbone.irc_addr);
     189        omap_irc_irq_ack(bbone.irc_addr);
    190190}
    191191
    … …  
    214214                indev_t *srln = srln_wire(srln_instance, sink);
    215215                omap_uart_input_wire(&bbone.uart, srln);
    216                 am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
     216                omap_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
    217217        }
    218218#endif

  • kernel/arch/arm32/src/mm/frame.c

    rf7a33de r0c2d9bb  
    8888void boot_page_table_free(void)
    8989{
    90         unsigned int i;
    91         for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++)
    92                 frame_free(i * FRAME_SIZE + BOOT_PAGE_TABLE_ADDRESS);
     90        frame_free(BOOT_PAGE_TABLE_ADDRESS,
     91            BOOT_PAGE_TABLE_SIZE_IN_FRAMES);
    9392}
    9493

  • kernel/arch/arm32/src/mm/page.c

    rf7a33de r0c2d9bb  
    6969#ifdef HIGH_EXCEPTION_VECTORS
    7070        /* Create mapping for exception table at high offset */
    71         uintptr_t ev_frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_NONE);
     71        uintptr_t ev_frame = frame_alloc(1, FRAME_NONE, 0);
    7272        page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, ev_frame, flags);
    7373#else

  • kernel/arch/arm32/src/ras.c

    rf7a33de r0c2d9bb  
    5151void ras_init(void)
    5252{
    53         uintptr_t frame;
    54 
    55         frame = (uintptr_t) frame_alloc(ONE_FRAME,
    56             FRAME_ATOMIC | FRAME_HIGHMEM);
     53        uintptr_t frame =
     54            frame_alloc(1, FRAME_ATOMIC | FRAME_HIGHMEM, 0);
    5755        if (!frame)
    58                 frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_LOWMEM);
     56                frame = frame_alloc(1, FRAME_LOWMEM, 0);
     57       
    5958        ras_page = (uintptr_t *) km_map(frame,
    6059            PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
    61 
     60       
    6261        memsetb(ras_page, PAGE_SIZE, 0);
    6362        ras_page[RAS_START] = 0;

  • kernel/arch/ia32/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4040
     41#define FRAME_LOWPRIO  0x1000
     42
    4143#ifndef __ASM__
    4244

  • kernel/arch/ia32/include/arch/mm/page.h

    rf7a33de r0c2d9bb  
    6666
    6767/* Page table sizes for each level. */
    68 #define PTL0_SIZE_ARCH  ONE_FRAME
    69 #define PTL1_SIZE_ARCH  0
    70 #define PTL2_SIZE_ARCH  0
    71 #define PTL3_SIZE_ARCH  ONE_FRAME
     68#define PTL0_FRAMES_ARCH  1
     69#define PTL1_FRAMES_ARCH  1
     70#define PTL2_FRAMES_ARCH  1
     71#define PTL3_FRAMES_ARCH  1
    7272
    7373/* Macros calculating indices for each level. */

  • kernel/arch/ia32/src/ddi/ddi.c

    rf7a33de r0c2d9bb  
    6868                 */
    6969               
    70                 void *store = malloc(bitmap_size(elements, 0), FRAME_ATOMIC);
     70                void *store = malloc(bitmap_size(elements), FRAME_ATOMIC);
    7171                if (!store)
    7272                        return ENOMEM;
    7373               
    7474                bitmap_t oldiomap;
    75                 bitmap_initialize(&oldiomap, task->arch.iomap.elements, 0,
     75                bitmap_initialize(&oldiomap, task->arch.iomap.elements,
    7676                    task->arch.iomap.bits);
    7777               
    78                 bitmap_initialize(&task->arch.iomap, elements, 0, store);
     78                bitmap_initialize(&task->arch.iomap, elements, store);
    7979               
    8080                /*
    … …  
    129129               
    130130                bitmap_t iomap;
    131                 bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, 0,
     131                bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
    132132                    CPU->arch.tss->iomap);
    133133                bitmap_copy(&iomap, &TASK->arch.iomap, elements);
    … …  
    157157       
    158158        descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
    159         size_t size = bitmap_size(elements, 0);
     159        size_t size = bitmap_size(elements);
    160160        gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
    161161        gdtr_load(&cpugdtr);

  • kernel/arch/ia32/src/mm/frame.c

    rf7a33de r0c2d9bb  
    4747
    4848#define PHYSMEM_LIMIT32  UINT64_C(0x100000000)
    49 #define PHYSMEM_LIMIT_DMA   UINT64_C(0x1000000)
    5049
    5150size_t hardcoded_unmapped_ktext_size = 0;
    … …  
    9291                                else
    9392                                        conf = minconf;
    94 
    95                                 if ((pfn * PAGE_SIZE) < PHYSMEM_LIMIT_DMA) {
    96                                         size_t dma_count = min(
    97                                             PHYSMEM_LIMIT_DMA / PAGE_SIZE - pfn,
    98                                             count);
    99                                         zone_create(pfn, dma_count, conf,
    100                                             ZONE_AVAILABLE | ZONE_DMA);
    101                                         count -= dma_count;
    102                                         pfn += dma_count;
    103                                 }
    104 
    105                                 conf = pfn;
    106                                 if (count) {
    107                                         zone_create(pfn, count, conf,
    108                                             ZONE_AVAILABLE | ZONE_LOWMEM);
    109                                 }
     93                                zone_create(pfn, count, conf,
     94                                    ZONE_AVAILABLE | ZONE_LOWMEM);
    11095                        } else {
    11196                                conf = zone_external_conf_alloc(count);
    112                                 if (conf != 0) {
     97                                if (conf != 0)
    11398                                        zone_create(pfn, count, conf,
    11499                                            ZONE_AVAILABLE | ZONE_HIGHMEM);
    115                                 }
    116100                        }
    117101                } else if ((e820table[i].type == MEMMAP_MEMORY_ACPI) ||

  • kernel/arch/ia32/src/proc/task.c

    rf7a33de r0c2d9bb  
    4646{
    4747        task->arch.iomapver = 0;
    48         bitmap_initialize(&task->arch.iomap, 0, 0, NULL);
     48        bitmap_initialize(&task->arch.iomap, 0, NULL);
    4949}
    5050

  • kernel/arch/ia64/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4040
     41#define FRAME_LOWPRIO  0
     42
    4143#ifndef __ASM__
    4244

  • kernel/arch/ia64/src/ddi/ddi.c

    rf7a33de r0c2d9bb  
    11/*
    22 * Copyright (c) 2006 Jakub Jermar
    3  * Copyright (c) 2008 Jakub vana
     3 * Copyright (c) 2008 Jakub Vana
    44 * All rights reserved.
    55 *
    … …  
    6060                        return ENOMEM;
    6161               
    62                 void *store = malloc(bitmap_size(IO_MEMMAP_PAGES, 0), 0);
     62                void *store = malloc(bitmap_size(IO_MEMMAP_PAGES), 0);
    6363                if (store == NULL)
    6464                        return ENOMEM;
    6565               
    66                 bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, 0, store);
     66                bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, store);
    6767                bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES);
    6868        }

  • kernel/arch/ia64/src/mm/vhpt.c

    rf7a33de r0c2d9bb  
    4242uintptr_t vhpt_set_up(void)
    4343{
    44         vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH,
    45             FRAME_KA | FRAME_ATOMIC);
    46         if (!vhpt_base)
     44        uintptr_t vhpt_frame =
     45            frame_alloc(SIZE2FRAMES(VHPT_SIZE), FRAME_ATOMIC, 0);
     46        if (!vhpt_frame)
    4747                panic("Kernel configured with VHPT but no memory for table.");
     48       
     49        vhpt_base = (vhpt_entry_t *) PA2KA(vhpt_frame);
    4850        vhpt_invalidate_all();
    4951        return (uintptr_t) vhpt_base;
    … …  
    8284void vhpt_invalidate_all()
    8385{
    84         memsetb(vhpt_base, 1 << VHPT_WIDTH, 0);
     86        memsetb(vhpt_base, VHPT_SIZE, 0);
    8587}
    8688

  • kernel/arch/mips32/include/arch/asm.h

    rf7a33de r0c2d9bb  
    4242NO_TRACE static inline void cpu_sleep(void)
    4343{
    44         /*
    45          * Unfortunatelly most of the simulators do not support
    46          *
    47          * asm volatile (
    48          *     "wait"
    49          * );
    50          *
    51          */
     44        asm volatile ("wait");
    5245}
    5346

  • kernel/arch/mips32/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4040
     41#define FRAME_LOWPRIO  0
     42
    4143#ifndef __ASM__
    4244

  • kernel/arch/mips32/include/arch/mm/page.h

    rf7a33de r0c2d9bb  
    2727 */
    2828
    29 /** @addtogroup mips32mm       
     29/** @addtogroup mips32mm
    3030 * @{
    3131 */
    … …  
    7070 * - PTL3 has 4096 entries (12 bits)
    7171 */
    72  
     72
    7373/* Macros describing number of entries in each level. */
    74 #define PTL0_ENTRIES_ARCH       64
    75 #define PTL1_ENTRIES_ARCH       0
    76 #define PTL2_ENTRIES_ARCH       0
    77 #define PTL3_ENTRIES_ARCH       4096
     74#define PTL0_ENTRIES_ARCH  64
     75#define PTL1_ENTRIES_ARCH  0
     76#define PTL2_ENTRIES_ARCH  0
     77#define PTL3_ENTRIES_ARCH  4096
    7878
    7979/* Macros describing size of page tables in each level. */
    80 #define PTL0_SIZE_ARCH          ONE_FRAME
    81 #define PTL1_SIZE_ARCH          0
    82 #define PTL2_SIZE_ARCH          0
    83 #define PTL3_SIZE_ARCH          ONE_FRAME
     80#define PTL0_FRAMES_ARCH  1
     81#define PTL1_FRAMES_ARCH  1
     82#define PTL2_FRAMES_ARCH  1
     83#define PTL3_FRAMES_ARCH  1
    8484
    8585/* Macros calculating entry indices for each level. */
    86 #define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
    87 #define PTL1_INDEX_ARCH(vaddr)  0
    88 #define PTL2_INDEX_ARCH(vaddr)  0
    89 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
     86#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
     87#define PTL1_INDEX_ARCH(vaddr)  0
     88#define PTL2_INDEX_ARCH(vaddr)  0
     89#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
    9090
    9191/* Set accessor for PTL0 address. */
    9292#define SET_PTL0_ADDRESS_ARCH(ptl0)
    9393
    94 /* Get PTE address accessors for each level. */ 
     94/* Get PTE address accessors for each level. */
    9595#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    9696        (((pte_t *) (ptl0))[(i)].pfn << 12)
    … …  
    196196        p->p = 1;
    197197}
    198        
    199198
    200199extern void page_arch_init(void);

  • kernel/arch/mips32/src/mach/malta/malta.c

    rf7a33de r0c2d9bb  
    103103void malta_input_init(void)
    104104{
     105        (void) stdin_wire();
    105106}
    106107

  • kernel/arch/mips32/src/mm/tlb.c

    rf7a33de r0c2d9bb  
    4848#include <symtab.h>
    4949
    50 #define PFN_SHIFT       12
    51 #define VPN_SHIFT       12
    52 #define ADDR2VPN(a)     ((a) >> VPN_SHIFT)
    53 #define ADDR2VPN2(a)    (ADDR2VPN((a)) >> 1)
    54 #define VPN2ADDR(vpn)   ((vpn) << VPN_SHIFT)
    55 #define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1)
    56 #define PFN2ADDR(pfn)   ((pfn) << PFN_SHIFT)
    57 
    58 #define BANK_SELECT_BIT(a)      (((a) >> PAGE_WIDTH) & 1)
    59        
     50#define PFN_SHIFT  12
     51#define VPN_SHIFT  12
     52
     53#define ADDR2HI_VPN(a)   ((a) >> VPN_SHIFT)
     54#define ADDR2HI_VPN2(a)  (ADDR2HI_VPN((a)) >> 1)
     55
     56#define HI_VPN2ADDR(vpn)    ((vpn) << VPN_SHIFT)
     57#define HI_VPN22ADDR(vpn2)  (HI_VPN2ADDR(vpn2) << 1)
     58
     59#define LO_PFN2ADDR(pfn)  ((pfn) << PFN_SHIFT)
     60
     61#define BANK_SELECT_BIT(a)  (((a) >> PAGE_WIDTH) & 1)
    6062
    6163/** Initialize TLB.
    … …  
    266268{
    267269        hi->value = 0;
    268         hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
     270        hi->vpn2 = ADDR2HI_VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
    269271        hi->asid = asid;
    270272}
    … …  
    295297               
    296298                printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
    297                     i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask,
    298                     lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn));
     299                    i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask,
     300                    lo0.g, lo0.v, lo0.d, lo0.c, LO_PFN2ADDR(lo0.pfn));
    299301                printf("                               %1u%1u%1u%1u  %0#10x\n",
    300                     lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn));
     302                    lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn));
    301303        }
    302304       

  • kernel/arch/mips64/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4040
     41#define FRAME_LOWPRIO  0
     42
    4143#ifndef __ASM__
    4244

  • kernel/arch/ppc32/include/arch/mm/frame.h

    rf7a33de r0c2d9bb  
    3939#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4040
     41#define FRAME_LOWPRIO  0
     42
    4143#ifndef __ASM__
    4244

  • kernel/arch/ppc32/include/arch/mm/page.h

    rf7a33de r0c2d9bb  
    7070
    7171/* Page table sizes for each level. */
    72 #define PTL0_SIZE_ARCH  ONE_FRAME
    73 #define PTL1_SIZE_ARCH  0
    74 #define PTL2_SIZE_ARCH  0
    75 #define PTL3_SIZE_ARCH  ONE_FRAME
     72#define PTL0_FRAMES_ARCH  1
     73#define PTL1_FRAMES_ARCH  1
     74#define PTL2_FRAMES_ARCH  1
     75#define PTL3_FRAMES_ARCH  1
    7676
    7777/* Macros calculating indices into page tables on each level. */

  • kernel/arch/sparc64/include/arch/mm/sun4u/frame.h

    rf7a33de r0c2d9bb  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    4141 * Therefore, the kernel uses 8K only internally on the TLB and TSB levels.
    4242 */
    43 #define MMU_FRAME_WIDTH         13      /* 8K */
    44 #define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
     43#define MMU_FRAME_WIDTH  13  /* 8K */
     44#define MMU_FRAME_SIZE   (1 << MMU_FRAME_WIDTH)
    4545
    4646/*
    … …  
    4949 * each 16K page with a pair of adjacent 8K pages.
    5050 */
    51 #define FRAME_WIDTH             14      /* 16K */
    52 #define FRAME_SIZE              (1 << FRAME_WIDTH)
     51#define FRAME_WIDTH  14  /* 16K */
     52#define FRAME_SIZE   (1 << FRAME_WIDTH)
     53
     54#define FRAME_LOWPRIO  0
    5355
    5456#ifndef __ASM__

  • kernel/arch/sparc64/include/arch/mm/sun4v/frame.h

    rf7a33de r0c2d9bb  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    3636#define KERN_sparc64_sun4v_FRAME_H_
    3737
    38 #define MMU_FRAME_WIDTH         13      /* 8K */
    39 #define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
     38#define MMU_FRAME_WIDTH  13  /* 8K */
     39#define MMU_FRAME_SIZE   (1 << MMU_FRAME_WIDTH)
    4040
    41 #define FRAME_WIDTH             13
    42 #define FRAME_SIZE              (1 << FRAME_WIDTH)
     41#define FRAME_WIDTH  13
     42#define FRAME_SIZE   (1 << FRAME_WIDTH)
     43
     44#define FRAME_LOWPRIO  0
    4345
    4446#endif

  • kernel/arch/sparc64/src/mm/sun4u/as.c

    rf7a33de r0c2d9bb  
    6363{
    6464#ifdef CONFIG_TSB
    65         /*
    66          * The order must be calculated with respect to the emulated
    67          * 16K page size.
    68          *
    69          */
    70         uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
    71             sizeof(tsb_entry_t)) >> FRAME_WIDTH);
    72        
    73         uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
    74        
    75         if (!tsb)
     65        uintptr_t tsb_phys =
     66            frame_alloc(SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
     67            sizeof(tsb_entry_t)), flags, 0);
     68        if (!tsb_phys)
    7669                return -1;
    7770       
    78         as->arch.itsb = (tsb_entry_t *) tsb;
    79         as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
     71        tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_phys);
     72       
     73        as->arch.itsb = tsb;
     74        as->arch.dtsb = tsb + ITSB_ENTRY_COUNT;
     75       
     76        memsetb(as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
     77            sizeof(tsb_entry_t), 0);
     78#endif
     79       
     80        return 0;
     81}
     82
     83int as_destructor_arch(as_t *as)
     84{
     85#ifdef CONFIG_TSB
     86        size_t frames = SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
    8087            sizeof(tsb_entry_t));
    81        
    82         memsetb(as->arch.itsb,
    83             (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
    84 #endif
    85        
    86         return 0;
    87 }
    88 
    89 int as_destructor_arch(as_t *as)
    90 {
    91 #ifdef CONFIG_TSB
    92         /*
    93          * The count must be calculated with respect to the emualted 16K page
    94          * size.
    95          */
    96         size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
    97             sizeof(tsb_entry_t)) >> FRAME_WIDTH;
    98         frame_free(KA2PA((uintptr_t) as->arch.itsb));
    99        
    100         return cnt;
     88        frame_free(KA2PA((uintptr_t) as->arch.itsb), frames);
     89       
     90        return frames;
    10191#else
    10292        return 0;

  • kernel/arch/sparc64/src/mm/sun4v/as.c

    rf7a33de r0c2d9bb  
    6666{
    6767#ifdef CONFIG_TSB
    68         uint8_t order = fnzb32(
    69                 (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH);
    70        
    71         uintptr_t tsb = (uintptr_t) frame_alloc(order, flags);
    72        
     68        uintptr_t tsb =
     69            frame_alloc(SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)),
     70            flags, 0);
    7371        if (!tsb)
    7472                return -1;
    … …  
    9290{
    9391#ifdef CONFIG_TSB
    94         size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
    95         frame_free((uintptr_t) as->arch.tsb_description.tsb_base);
     92        size_t frames = SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t));
     93        frame_free(as->arch.tsb_description.tsb_base, frames);
    9694       
    97         return cnt;
     95        return frames;
    9896#else
    9997        return 0;
Note: See TracChangeset for help on using the changeset viewer.