Changeset 0b9ac3c in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2010-02-23T19:03:28Z (16 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c62d2e1
Parents:
1ccafee (diff), 5e50394 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/sparc64/include
Files:
33 added
19 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch.h

    r1ccafee r0b9ac3c  
    3838#define KERN_sparc64_ARCH_H_
    3939
     40#if defined (SUN4U)
     41#include <arch/sun4u/arch.h>
     42#elif defined (SUN4V)
     43#include <arch/sun4v/arch.h>
     44#endif
     45
    4046#define ASI_AIUP                0x10    /** Access to primary context with user privileges. */
    4147#define ASI_AIUS                0x11    /** Access to secondary context with user privileges. */
    42 #define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
    43 #define ASI_DCACHE_TAG          0x47    /** ASI D-Cache Tag. */
    44 #define ASI_ICBUS_CONFIG                0x4a    /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
    4548
    4649#define NWINDOWS                8       /** Number of register window sets. */
    … …  
    5255#endif /* __ASM__ */
    5356
     57
    5458#endif
    5559

  • kernel/arch/sparc64/include/asm.h

    r1ccafee r0b9ac3c  
    430430}
    431431
    432 extern void cpu_halt(void);
     432extern void cpu_halt(void) __attribute__((noreturn));
    433433extern void cpu_sleep(void);
    434434extern void asm_delay_loop(const uint32_t usec);

  • kernel/arch/sparc64/include/atomic.h

    r1ccafee r0b9ac3c  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    4545 *
    4646 * @param val Atomic variable.
    47  * @param i Signed value to be added.
     47 * @param i   Signed value to be added.
    4848 *
    4949 * @return Value of the atomic variable as it existed before addition.
     50 *
    5051 */
    51 static inline long atomic_add(atomic_t *val, int i)
     52static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
    5253{
    53         uint64_t a, b;
    54 
     54        atomic_count_t a;
     55        atomic_count_t b;
     56       
    5557        do {
    56                 volatile uintptr_t x = (uint64_t) &val->count;
    57 
    58                 a = *((uint64_t *) x);
     58                volatile uintptr_t ptr = (uintptr_t) &val->count;
     59               
     60                a = *((atomic_count_t *) ptr);
    5961                b = a + i;
    60                 asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)),
    61                     "+r" (b) : "r" (a));
     62               
     63                asm volatile (
     64                        "casx %0, %2, %1\n"
     65                        : "+m" (*((atomic_count_t *) ptr)),
     66                      "+r" (b)
     67                    : "r" (a)
     68                );
    6269        } while (a != b);
    63 
     70       
    6471        return a;
    6572}
    6673
    67 static inline long atomic_preinc(atomic_t *val)
     74static inline atomic_count_t atomic_preinc(atomic_t *val)
    6875{
    6976        return atomic_add(val, 1) + 1;
    7077}
    7178
    72 static inline long atomic_postinc(atomic_t *val)
     79static inline atomic_count_t atomic_postinc(atomic_t *val)
    7380{
    7481        return atomic_add(val, 1);
    7582}
    7683
    77 static inline long atomic_predec(atomic_t *val)
     84static inline atomic_count_t atomic_predec(atomic_t *val)
    7885{
    7986        return atomic_add(val, -1) - 1;
    8087}
    8188
    82 static inline long atomic_postdec(atomic_t *val)
     89static inline atomic_count_t atomic_postdec(atomic_t *val)
    8390{
    8491        return atomic_add(val, -1);
    … …  
    95102}
    96103
    97 static inline long test_and_set(atomic_t *val)
     104static inline atomic_count_t test_and_set(atomic_t *val)
    98105{
    99         uint64_t v = 1;
    100         volatile uintptr_t x = (uint64_t) &val->count;
    101 
    102         asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)),
    103             "+r" (v) : "r" (0));
    104 
     106        atomic_count_t v = 1;
     107        volatile uintptr_t ptr = (uintptr_t) &val->count;
     108       
     109        asm volatile (
     110                "casx %0, %2, %1\n"
     111                : "+m" (*((atomic_count_t *) ptr)),
     112              "+r" (v)
     113            : "r" (0)
     114        );
     115       
    105116        return v;
    106117}
    … …  
    108119static inline void atomic_lock_arch(atomic_t *val)
    109120{
    110         uint64_t tmp1 = 1;
    111         uint64_t tmp2 = 0;
    112 
    113         volatile uintptr_t x = (uint64_t) &val->count;
    114 
     121        atomic_count_t tmp1 = 1;
     122        atomic_count_t tmp2 = 0;
     123       
     124        volatile uintptr_t ptr = (uintptr_t) &val->count;
     125       
    115126        preemption_disable();
    116 
     127       
    117128        asm volatile (
    118         "0:\n"
    119                 "casx %0, %3, %1\n"
    120                 "brz %1, 2f\n"
    121                 "nop\n"
    122         "1:\n"
    123                 "ldx %0, %2\n"
    124                 "brz %2, 0b\n"
    125                 "nop\n"
    126                 "ba %%xcc, 1b\n"
    127                 "nop\n"
    128         "2:\n"
    129                 : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
     129                "0:\n"
     130                        "casx %0, %3, %1\n"
     131                        "brz %1, 2f\n"
     132                        "nop\n"
     133                "1:\n"
     134                        "ldx %0, %2\n"
     135                        "brz %2, 0b\n"
     136                        "nop\n"
     137                        "ba %%xcc, 1b\n"
     138                        "nop\n"
     139                "2:\n"
     140                : "+m" (*((atomic_count_t *) ptr)),
     141                  "+r" (tmp1),
     142                  "+r" (tmp2)
     143                : "r" (0)
    130144        );
    131145       

  • kernel/arch/sparc64/include/context.h

    r1ccafee r0b9ac3c  
    4242#define SP_DELTA        (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE)
    4343
    44 #ifdef context_set
    45 #undef context_set
    46 #endif
    47 
    4844#define context_set(c, _pc, stack, size)                        \
    4945        (c)->pc = ((uintptr_t) _pc) - 8;                        \

  • kernel/arch/sparc64/include/cpu.h

    r1ccafee r0b9ac3c  
    6464#endif
    6565
    66 typedef struct {
    67         uint32_t mid;                   /**< Processor ID as read from
    68                                              UPA_CONFIG/FIREPLANE_CONFIG. */
    69         ver_reg_t ver;
    70         uint32_t clock_frequency;       /**< Processor frequency in Hz. */
    71         uint64_t next_tick_cmpr;        /**< Next clock interrupt should be
    72                                              generated when the TICK register
    73                                              matches this value. */
    74 } cpu_arch_t;
    7566
     67#if defined (SUN4U)
     68#include <arch/sun4u/cpu.h>
     69#elif defined (SUN4V)
     70#include <arch/sun4v/cpu.h>
     71#endif
    7672
    77 /**
    78  * Reads the module ID (agent ID/CPUID) of the current CPU.
    79  */
    80 static inline uint32_t read_mid(void)
    81 {
    82         uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
    83         icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
    84 #if defined (US)
    85         return icbus_config & 0x1f;
    86 #elif defined (US3)
    87         if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)
    88                 return icbus_config & 0x1f;
    89         else
    90                 return icbus_config & 0x3ff;
    91 #endif
    92 }
    9373
    9474#endif 

  • kernel/arch/sparc64/include/drivers/tick.h

    r1ccafee r0b9ac3c  
    3636#define KERN_sparc64_TICK_H_
    3737
     38#include <arch/asm.h>
    3839#include <arch/interrupt.h>
     40
     41/* mask of the "counter" field of the Tick register */
     42#define TICK_COUNTER_MASK       (~(1l << 63))
    3943
    4044extern void tick_init(void);
    4145extern void tick_interrupt(int n, istate_t *istate);
     46
     47/**
     48 * Reads the Tick register counter.
     49 */
     50static inline uint64_t tick_counter_read(void)
     51{
     52        return TICK_COUNTER_MASK & tick_read();
     53}
    4254
    4355#endif

  • kernel/arch/sparc64/include/memstr.h

    r1ccafee r0b9ac3c  
    3838#define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
    3939
    40 extern void memsetw(void *dst, size_t cnt, uint16_t x);
    41 extern void memsetb(void *dst, size_t cnt, uint8_t x);
    42 
    43 extern int memcmp(const void *a, const void *b, size_t cnt);
     40extern void memsetw(void *, size_t, uint16_t);
     41extern void memsetb(void *, size_t, uint8_t);
    4442
    4543#endif

  • kernel/arch/sparc64/include/mm/as.h

    r1ccafee r0b9ac3c  
    3636#define KERN_sparc64_AS_H_
    3737
    38 #include <arch/mm/tte.h>
    39 
    40 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      1
    41 
    42 #define KERNEL_ADDRESS_SPACE_START_ARCH         (unsigned long) 0x0000000000000000
    43 #define KERNEL_ADDRESS_SPACE_END_ARCH           (unsigned long) 0xffffffffffffffff
    44 #define USER_ADDRESS_SPACE_START_ARCH           (unsigned long) 0x0000000000000000
    45 #define USER_ADDRESS_SPACE_END_ARCH             (unsigned long) 0xffffffffffffffff
    46 
    47 #define USTACK_ADDRESS_ARCH     (0xffffffffffffffffULL - (PAGE_SIZE - 1))
    48 
    49 #ifdef CONFIG_TSB
    50 
    51 /** TSB Tag Target register. */
    52 typedef union tsb_tag_target {
    53         uint64_t value;
    54         struct {
    55                 unsigned invalid : 1;   /**< Invalidated by software. */
    56                 unsigned : 2;
    57                 unsigned context : 13;  /**< Software ASID. */
    58                 unsigned : 6;
    59                 uint64_t va_tag : 42;   /**< Virtual address bits <63:22>. */
    60         } __attribute__ ((packed));
    61 } tsb_tag_target_t;
    62 
    63 /** TSB entry. */
    64 typedef struct tsb_entry {
    65         tsb_tag_target_t tag;
    66         tte_data_t data;
    67 } __attribute__ ((packed)) tsb_entry_t;
    68 
    69 typedef struct {
    70         tsb_entry_t *itsb;
    71         tsb_entry_t *dtsb;
    72 } as_arch_t;
    73 
    74 #else
    75 
    76 typedef struct {
    77 } as_arch_t;
    78 
    79 #endif /* CONFIG_TSB */
    80 
    81 #include <genarch/mm/as_ht.h>
    82 
    83 #ifdef CONFIG_TSB
    84 #include <arch/mm/tsb.h>
    85 #define as_invalidate_translation_cache(as, page, cnt) \
    86         tsb_invalidate((as), (page), (cnt))
    87 #else
    88 #define as_invalidate_translation_cache(as, page, cnt)
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/as.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/as.h>
    8942#endif
    90 
    91 extern void as_arch_init(void);
    9243
    9344#endif

  • kernel/arch/sparc64/include/mm/frame.h

    r1ccafee r0b9ac3c  
    3636#define KERN_sparc64_FRAME_H_
    3737
    38 /*
    39  * Page size supported by the MMU.
    40  * For 8K there is the nasty illegal virtual aliasing problem.
    41  * Therefore, the kernel uses 8K only internally on the TLB and TSB levels.
    42  */
    43 #define MMU_FRAME_WIDTH         13      /* 8K */
    44 #define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
    45 
    46 /*
    47  * Page size exported to the generic memory management subsystems.
    48  * This page size is not directly supported by the MMU, but we can emulate
    49  * each 16K page with a pair of adjacent 8K pages.
    50  */
    51 #define FRAME_WIDTH             14      /* 16K */
    52 #define FRAME_SIZE              (1 << FRAME_WIDTH)
    53 
    54 #ifdef KERNEL
    55 #ifndef __ASM__
    56 
    57 #include <arch/types.h>
    58 
    59 union frame_address {
    60         uintptr_t address;
    61         struct {
    62 #if defined (US)
    63                 unsigned : 23;
    64                 uint64_t pfn : 28;              /**< Physical Frame Number. */
    65 #elif defined (US3)
    66                 unsigned : 21;
    67                 uint64_t pfn : 30;              /**< Physical Frame Number. */
    68 #endif
    69                 unsigned offset : 13;           /**< Offset. */
    70         } __attribute__ ((packed));
    71 };
    72 
    73 typedef union frame_address frame_address_t;
    74 
    75 extern uintptr_t last_frame;
    76 extern uintptr_t end_of_identity;
    77 
    78 extern void frame_arch_init(void);
    79 #define physmem_print()
    80 
    81 #endif
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/frame.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/frame.h>
    8242#endif
    8343

  • kernel/arch/sparc64/include/mm/mmu.h

    r1ccafee r0b9ac3c  
    3636#define KERN_sparc64_MMU_H_
    3737
    38 #if defined(US)
    39 /* LSU Control Register ASI. */
    40 #define ASI_LSU_CONTROL_REG             0x45    /**< Load/Store Unit Control Register. */
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/mmu.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/mmu.h>
    4142#endif
    4243
    43 /* I-MMU ASIs. */
    44 #define ASI_IMMU                        0x50
    45 #define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
    46 #define ASI_IMMU_TSB_64KB_PTR_REG       0x52
    47 #define ASI_ITLB_DATA_IN_REG            0x54
    48 #define ASI_ITLB_DATA_ACCESS_REG        0x55
    49 #define ASI_ITLB_TAG_READ_REG           0x56
    50 #define ASI_IMMU_DEMAP                  0x57
    51 
    52 /* Virtual Addresses within ASI_IMMU. */
    53 #define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
    54 #define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    55 #define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
    56 #define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
    57 #if defined (US3)
    58 #define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
    59 #define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
    60 #endif
    61 
    62 
    63 /* D-MMU ASIs. */
    64 #define ASI_DMMU                        0x58
    65 #define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
    66 #define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
    67 #define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
    68 #define ASI_DTLB_DATA_IN_REG            0x5c
    69 #define ASI_DTLB_DATA_ACCESS_REG        0x5d
    70 #define ASI_DTLB_TAG_READ_REG           0x5e
    71 #define ASI_DMMU_DEMAP                  0x5f
    72 
    73 /* Virtual Addresses within ASI_DMMU. */
    74 #define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
    75 #define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
    76 #define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
    77 #define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
    78 #define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
    79 #define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
    80 #define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
    81 #define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
    82 #define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
    83 #if defined (US3)
    84 #define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
    85 #define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
    86 #define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
    87 #endif
    88 
    89 #ifndef __ASM__
    90 
    91 #include <arch/asm.h>
    92 #include <arch/barrier.h>
    93 #include <arch/types.h>
    94 
    95 #if defined(US)
    96 /** LSU Control Register. */
    97 typedef union {
    98         uint64_t value;
    99         struct {
    100                 unsigned : 23;
    101                 unsigned pm : 8;
    102                 unsigned vm : 8;
    103                 unsigned pr : 1;
    104                 unsigned pw : 1;
    105                 unsigned vr : 1;
    106                 unsigned vw : 1;
    107                 unsigned : 1;
    108                 unsigned fm : 16;       
    109                 unsigned dm : 1;        /**< D-MMU enable. */
    110                 unsigned im : 1;        /**< I-MMU enable. */
    111                 unsigned dc : 1;        /**< D-Cache enable. */
    112                 unsigned ic : 1;        /**< I-Cache enable. */
    113                
    114         } __attribute__ ((packed));
    115 } lsu_cr_reg_t;
    116 #endif /* US */
    117 
    118 #endif /* !def __ASM__ */
    11944
    12045#endif

  • kernel/arch/sparc64/include/mm/tlb.h

    r1ccafee r0b9ac3c  
    3636#define KERN_sparc64_TLB_H_
    3737
    38 #if defined (US)
    39 #define ITLB_ENTRY_COUNT                64
    40 #define DTLB_ENTRY_COUNT                64
    41 #define DTLB_MAX_LOCKED_ENTRIES         DTLB_ENTRY_COUNT
     38
     39#if defined (SUN4U)
     40#include <arch/mm/sun4u/tlb.h>
     41#elif defined (SUN4V)
     42#include <arch/mm/sun4v/tlb.h>
    4243#endif
    43 
    44 /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
    45 #if defined (US3)
    46 #define DTLB_MAX_LOCKED_ENTRIES         16
    47 #endif
    48 
    49 #define MEM_CONTEXT_KERNEL              0
    50 #define MEM_CONTEXT_TEMP                1
    51 
    52 /** Page sizes. */
    53 #define PAGESIZE_8K     0
    54 #define PAGESIZE_64K    1
    55 #define PAGESIZE_512K   2
    56 #define PAGESIZE_4M     3
    57 
    58 /** Bit width of the TLB-locked portion of kernel address space. */
    59 #define KERNEL_PAGE_WIDTH       22      /* 4M */
    60 
    61 /* TLB Demap Operation types. */
    62 #define TLB_DEMAP_PAGE          0
    63 #define TLB_DEMAP_CONTEXT       1
    64 #if defined (US3)
    65 #define TLB_DEMAP_ALL           2
    66 #endif
    67 
    68 #define TLB_DEMAP_TYPE_SHIFT    6
    69 
    70 /* TLB Demap Operation Context register encodings. */
    71 #define TLB_DEMAP_PRIMARY       0
    72 #define TLB_DEMAP_SECONDARY     1
    73 #define TLB_DEMAP_NUCLEUS       2
    74 
    75 /* There are more TLBs in one MMU in US3, their codes are defined here. */
    76 #if defined (US3)
    77 /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
    78 #define TLB_DSMALL      0
    79 #define TLB_DBIG_0      2
    80 #define TLB_DBIG_1      3
    81        
    82 /* I-MMU: one small (16-entry) TLB and one big TLB */
    83 #define TLB_ISMALL      0
    84 #define TLB_IBIG        2
    85 #endif
    86 
    87 #define TLB_DEMAP_CONTEXT_SHIFT 4
    88 
    89 /* TLB Tag Access shifts */
    90 #define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
    91 #define TLB_TAG_ACCESS_CONTEXT_MASK     ((1 << 13) - 1)
    92 #define TLB_TAG_ACCESS_VPN_SHIFT        13
    93 
    94 #ifndef __ASM__
    95 
    96 #include <arch/mm/tte.h>
    97 #include <arch/mm/mmu.h>
    98 #include <arch/mm/page.h>
    99 #include <arch/asm.h>
    100 #include <arch/barrier.h>
    101 #include <arch/types.h>
    102 #include <arch/register.h>
    103 #include <arch/cpu.h>
    104 
    105 union tlb_context_reg {
    106         uint64_t v;
    107         struct {
    108                 unsigned long : 51;
    109                 unsigned context : 13;          /**< Context/ASID. */
    110         } __attribute__ ((packed));
    111 };
    112 typedef union tlb_context_reg tlb_context_reg_t;
    113 
    114 /** I-/D-TLB Data In/Access Register type. */
    115 typedef tte_data_t tlb_data_t;
    116 
    117 /** I-/D-TLB Data Access Address in Alternate Space. */
    118 
    119 #if defined (US)
    120 
    121 union tlb_data_access_addr {
    122         uint64_t value;
    123         struct {
    124                 uint64_t : 55;
    125                 unsigned tlb_entry : 6;
    126                 unsigned : 3;
    127         } __attribute__ ((packed));
    128 };
    129 typedef union tlb_data_access_addr dtlb_data_access_addr_t;
    130 typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
    131 typedef union tlb_data_access_addr itlb_data_access_addr_t;
    132 typedef union tlb_data_access_addr itlb_tag_read_addr_t;
    133 
    134 #elif defined (US3)
    135 
    136 /*
    137  * In US3, I-MMU and D-MMU have different formats of the data
    138  * access register virtual address. In the corresponding
    139  * structures the member variable for the entry number is
    140  * called "local_tlb_entry" - it contrasts with the "tlb_entry"
    141  * for the US data access register VA structure. The rationale
    142  * behind this is to prevent careless mistakes in the code
    143  * caused by setting only the entry number and not the TLB
    144  * number in the US3 code (when taking the code from US).
    145  */
    146 
    147 union dtlb_data_access_addr {
    148         uint64_t value;
    149         struct {
    150                 uint64_t : 45;
    151                 unsigned : 1;
    152                 unsigned tlb_number : 2;
    153                 unsigned : 4;
    154                 unsigned local_tlb_entry : 9;
    155                 unsigned : 3;
    156         } __attribute__ ((packed));
    157 };
    158 typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
    159 typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
    160 
    161 union itlb_data_access_addr {
    162         uint64_t value;
    163         struct {
    164                 uint64_t : 45;
    165                 unsigned : 1;
    166                 unsigned tlb_number : 2;
    167                 unsigned : 6;
    168                 unsigned local_tlb_entry : 7;
    169                 unsigned : 3;
    170         } __attribute__ ((packed));
    171 };
    172 typedef union itlb_data_access_addr itlb_data_access_addr_t;
    173 typedef union itlb_data_access_addr itlb_tag_read_addr_t;
    174 
    175 #endif
    176 
    177 /** I-/D-TLB Tag Read Register. */
    178 union tlb_tag_read_reg {
    179         uint64_t value;
    180         struct {
    181                 uint64_t vpn : 51;      /**< Virtual Address bits 63:13. */
    182                 unsigned context : 13;  /**< Context identifier. */
    183         } __attribute__ ((packed));
    184 };
    185 typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
    186 typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
    187 
    188 
    189 /** TLB Demap Operation Address. */
    190 union tlb_demap_addr {
    191         uint64_t value;
    192         struct {
    193                 uint64_t vpn: 51;       /**< Virtual Address bits 63:13. */
    194 #if defined (US)
    195                 unsigned : 6;           /**< Ignored. */
    196                 unsigned type : 1;      /**< The type of demap operation. */
    197 #elif defined (US3)
    198                 unsigned : 5;           /**< Ignored. */
    199                 unsigned type: 2;       /**< The type of demap operation. */
    200 #endif
    201                 unsigned context : 2;   /**< Context register selection. */
    202                 unsigned : 4;           /**< Zero. */
    203         } __attribute__ ((packed));
    204 };
    205 typedef union tlb_demap_addr tlb_demap_addr_t;
    206 
    207 /** TLB Synchronous Fault Status Register. */
    208 union tlb_sfsr_reg {
    209         uint64_t value;
    210         struct {
    211 #if defined (US)
    212                 unsigned long : 40;     /**< Implementation dependent. */
    213                 unsigned asi : 8;       /**< ASI. */
    214                 unsigned : 2;
    215                 unsigned ft : 7;        /**< Fault type. */
    216 #elif defined (US3)
    217                 unsigned long : 39;     /**< Implementation dependent. */
    218                 unsigned nf : 1;        /**< Non-faulting load. */
    219                 unsigned asi : 8;       /**< ASI. */
    220                 unsigned tm : 1;        /**< I-TLB miss. */
    221                 unsigned : 3;           /**< Reserved. */
    222                 unsigned ft : 5;        /**< Fault type. */
    223 #endif
    224                 unsigned e : 1;         /**< Side-effect bit. */
    225                 unsigned ct : 2;        /**< Context Register selection. */
    226                 unsigned pr : 1;        /**< Privilege bit. */
    227                 unsigned w : 1;         /**< Write bit. */
    228                 unsigned ow : 1;        /**< Overwrite bit. */
    229                 unsigned fv : 1;        /**< Fault Valid bit. */
    230         } __attribute__ ((packed));
    231 };
    232 typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
    233 
    234 #if defined (US3)
    235 
    236 /*
    237  * Functions for determining the number of entries in TLBs. They either return
    238  * a constant value or a value based on the CPU autodetection.
    239  */
    240 
    241 /**
    242  * Determine the number of entries in the DMMU's small TLB.
    243  */
    244 static inline uint16_t tlb_dsmall_size(void)
    245 {
    246         return 16;
    247 }
    248 
    249 /**
    250  * Determine the number of entries in each DMMU's big TLB.
    251  */
    252 static inline uint16_t tlb_dbig_size(void)
    253 {
    254         return 512;
    255 }
    256 
    257 /**
    258  * Determine the number of entries in the IMMU's small TLB.
    259  */
    260 static inline uint16_t tlb_ismall_size(void)
    261 {
    262         return 16;
    263 }
    264 
    265 /**
    266  * Determine the number of entries in the IMMU's big TLB.
    267  */
    268 static inline uint16_t tlb_ibig_size(void)
    269 {
    270         if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
    271                 return 512;
    272         else
    273                 return 128;
    274 }
    275 
    276 #endif
    277 
    278 /** Read MMU Primary Context Register.
    279  *
    280  * @return              Current value of Primary Context Register.
    281  */
    282 static inline uint64_t mmu_primary_context_read(void)
    283 {
    284         return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
    285 }
    286 
    287 /** Write MMU Primary Context Register.
    288  *
    289  * @param v             New value of Primary Context Register.
    290  */
    291 static inline void mmu_primary_context_write(uint64_t v)
    292 {
    293         asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    294         flush_pipeline();
    295 }
    296 
    297 /** Read MMU Secondary Context Register.
    298  *
    299  * @return              Current value of Secondary Context Register.
    300  */
    301 static inline uint64_t mmu_secondary_context_read(void)
    302 {
    303         return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
    304 }
    305 
    306 /** Write MMU Primary Context Register.
    307  *
    308  * @param v             New value of Primary Context Register.
    309  */
    310 static inline void mmu_secondary_context_write(uint64_t v)
    311 {
    312         asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    313         flush_pipeline();
    314 }
    315 
    316 #if defined (US)
    317 
    318 /** Read IMMU TLB Data Access Register.
    319  *
    320  * @param entry         TLB Entry index.
    321  *
    322  * @return              Current value of specified IMMU TLB Data Access
    323  *                      Register.
    324  */
    325 static inline uint64_t itlb_data_access_read(size_t entry)
    326 {
    327         itlb_data_access_addr_t reg;
    328        
    329         reg.value = 0;
    330         reg.tlb_entry = entry;
    331         return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
    332 }
    333 
    334 /** Write IMMU TLB Data Access Register.
    335  *
    336  * @param entry         TLB Entry index.
    337  * @param value         Value to be written.
    338  */
    339 static inline void itlb_data_access_write(size_t entry, uint64_t value)
    340 {
    341         itlb_data_access_addr_t reg;
    342        
    343         reg.value = 0;
    344         reg.tlb_entry = entry;
    345         asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    346         flush_pipeline();
    347 }
    348 
    349 /** Read DMMU TLB Data Access Register.
    350  *
    351  * @param entry         TLB Entry index.
    352  *
    353  * @return              Current value of specified DMMU TLB Data Access
    354  *                      Register.
    355  */
    356 static inline uint64_t dtlb_data_access_read(size_t entry)
    357 {
    358         dtlb_data_access_addr_t reg;
    359        
    360         reg.value = 0;
    361         reg.tlb_entry = entry;
    362         return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
    363 }
    364 
    365 /** Write DMMU TLB Data Access Register.
    366  *
    367  * @param entry         TLB Entry index.
    368  * @param value         Value to be written.
    369  */
    370 static inline void dtlb_data_access_write(size_t entry, uint64_t value)
    371 {
    372         dtlb_data_access_addr_t reg;
    373        
    374         reg.value = 0;
    375         reg.tlb_entry = entry;
    376         asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    377         membar();
    378 }
    379 
    380 /** Read IMMU TLB Tag Read Register.
    381  *
    382  * @param entry         TLB Entry index.
    383  *
    384  * @return              Current value of specified IMMU TLB Tag Read Register.
    385  */
    386 static inline uint64_t itlb_tag_read_read(size_t entry)
    387 {
    388         itlb_tag_read_addr_t tag;
    389 
    390         tag.value = 0;
    391         tag.tlb_entry = entry;
    392         return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
    393 }
    394 
    395 /** Read DMMU TLB Tag Read Register.
    396  *
    397  * @param entry         TLB Entry index.
    398  *
    399  * @return              Current value of specified DMMU TLB Tag Read Register.
    400  */
    401 static inline uint64_t dtlb_tag_read_read(size_t entry)
    402 {
    403         dtlb_tag_read_addr_t tag;
    404 
    405         tag.value = 0;
    406         tag.tlb_entry = entry;
    407         return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
    408 }
    409 
    410 #elif defined (US3)
    411 
    412 
    413 /** Read IMMU TLB Data Access Register.
    414  *
    415  * @param tlb           TLB number (one of TLB_ISMALL or TLB_IBIG)
    416  * @param entry         TLB Entry index.
    417  *
    418  * @return              Current value of specified IMMU TLB Data Access
    419  *                      Register.
    420  */
    421 static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
    422 {
    423         itlb_data_access_addr_t reg;
    424        
    425         reg.value = 0;
    426         reg.tlb_number = tlb;
    427         reg.local_tlb_entry = entry;
    428         return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
    429 }
    430 
    431 /** Write IMMU TLB Data Access Register.
    432  * @param tlb           TLB number (one of TLB_ISMALL or TLB_IBIG)
    433  * @param entry         TLB Entry index.
    434  * @param value         Value to be written.
    435  */
    436 static inline void itlb_data_access_write(int tlb, size_t entry,
    437         uint64_t value)
    438 {
    439         itlb_data_access_addr_t reg;
    440        
    441         reg.value = 0;
    442         reg.tlb_number = tlb;
    443         reg.local_tlb_entry = entry;
    444         asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    445         flush_pipeline();
    446 }
    447 
    448 /** Read DMMU TLB Data Access Register.
    449  *
    450  * @param tlb           TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
    451  * @param entry         TLB Entry index.
    452  *
    453  * @return              Current value of specified DMMU TLB Data Access
    454  *                      Register.
    455  */
    456 static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
    457 {
    458         dtlb_data_access_addr_t reg;
    459        
    460         reg.value = 0;
    461         reg.tlb_number = tlb;
    462         reg.local_tlb_entry = entry;
    463         return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
    464 }
    465 
    466 /** Write DMMU TLB Data Access Register.
    467  *
    468  * @param tlb           TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) 
    469  * @param entry         TLB Entry index.
    470  * @param value         Value to be written.
    471  */
    472 static inline void dtlb_data_access_write(int tlb, size_t entry,
    473         uint64_t value)
    474 {
    475         dtlb_data_access_addr_t reg;
    476        
    477         reg.value = 0;
    478         reg.tlb_number = tlb;
    479         reg.local_tlb_entry = entry;
    480         asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    481         membar();
    482 }
    483 
    484 /** Read IMMU TLB Tag Read Register.
    485  *
    486  * @param tlb           TLB number (one of TLB_ISMALL or TLB_IBIG)
    487  * @param entry         TLB Entry index.
    488  *
    489  * @return              Current value of specified IMMU TLB Tag Read Register.
    490  */
    491 static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
    492 {
    493         itlb_tag_read_addr_t tag;
    494 
    495         tag.value = 0;
    496         tag.tlb_number = tlb;
    497         tag.local_tlb_entry = entry;
    498         return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
    499 }
    500 
    501 /** Read DMMU TLB Tag Read Register.
    502  *
    503  * @param tlb           TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
    504  * @param entry         TLB Entry index.
    505  *
    506  * @return              Current value of specified DMMU TLB Tag Read Register.
    507  */
    508 static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
    509 {
    510         dtlb_tag_read_addr_t tag;
    511 
    512         tag.value = 0;
    513         tag.tlb_number = tlb;
    514         tag.local_tlb_entry = entry;
    515         return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
    516 }
    517 
    518 #endif
    519 
    520 
    521 /** Write IMMU TLB Tag Access Register.
    522  *
    523  * @param v             Value to be written.
    524  */
    525 static inline void itlb_tag_access_write(uint64_t v)
    526 {
    527         asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    528         flush_pipeline();
    529 }
    530 
    531 /** Read IMMU TLB Tag Access Register.
    532  *
    533  * @return              Current value of IMMU TLB Tag Access Register.
    534  */
    535 static inline uint64_t itlb_tag_access_read(void)
    536 {
    537         return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
    538 }
    539 
    540 /** Write DMMU TLB Tag Access Register.
    541  *
    542  * @param v             Value to be written.
    543  */
    544 static inline void dtlb_tag_access_write(uint64_t v)
    545 {
    546         asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    547         membar();
    548 }
    549 
    550 /** Read DMMU TLB Tag Access Register.
    551  *
    552  * @return              Current value of DMMU TLB Tag Access Register.
    553  */
    554 static inline uint64_t dtlb_tag_access_read(void)
    555 {
    556         return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
    557 }
    558 
    559 
    560 /** Write IMMU TLB Data in Register.
    561  *
    562  * @param v             Value to be written.
    563  */
    564 static inline void itlb_data_in_write(uint64_t v)
    565 {
    566         asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    567         flush_pipeline();
    568 }
    569 
    570 /** Write DMMU TLB Data in Register.
    571  *
    572  * @param v             Value to be written.
    573  */
    574 static inline void dtlb_data_in_write(uint64_t v)
    575 {
    576         asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    577         membar();
    578 }
    579 
    580 /** Read ITLB Synchronous Fault Status Register.
    581  *
    582  * @return              Current content of I-SFSR register.
    583  */
    584 static inline uint64_t itlb_sfsr_read(void)
    585 {
    586         return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
    587 }
    588 
    589 /** Write ITLB Synchronous Fault Status Register.
    590  *
    591  * @param v             New value of I-SFSR register.
    592  */
    593 static inline void itlb_sfsr_write(uint64_t v)
    594 {
    595         asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    596         flush_pipeline();
    597 }
    598 
    599 /** Read DTLB Synchronous Fault Status Register.
    600  *
    601  * @return              Current content of D-SFSR register.
    602  */
    603 static inline uint64_t dtlb_sfsr_read(void)
    604 {
    605         return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
    606 }
    607 
    608 /** Write DTLB Synchronous Fault Status Register.
    609  *
    610  * @param v             New value of D-SFSR register.
    611  */
    612 static inline void dtlb_sfsr_write(uint64_t v)
    613 {
    614         asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    615         membar();
    616 }
    617 
    618 /** Read DTLB Synchronous Fault Address Register.
    619  *
    620  * @return              Current content of D-SFAR register.
    621  */
    622 static inline uint64_t dtlb_sfar_read(void)
    623 {
    624         return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
    625 }
    626 
    627 /** Perform IMMU TLB Demap Operation.
    628  *
    629  * @param type          Selects between context and page demap (and entire MMU
    630  *                      demap on US3).
    631  * @param context_encoding Specifies which Context register has Context ID for
    632  *                      demap.
    633  * @param page          Address which is on the page to be demapped.
    634  */
    635 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
    636 {
    637         tlb_demap_addr_t da;
    638         page_address_t pg;
    639        
    640         da.value = 0;
    641         pg.address = page;
    642        
    643         da.type = type;
    644         da.context = context_encoding;
    645         da.vpn = pg.vpn;
    646        
    647         /* da.value is the address within the ASI */
    648         asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
    649 
    650         flush_pipeline();
    651 }
    652 
    653 /** Perform DMMU TLB Demap Operation.
    654  *
    655  * @param type          Selects between context and page demap (and entire MMU
    656  *                      demap on US3).
    657  * @param context_encoding Specifies which Context register has Context ID for
    658  *                      demap.
    659  * @param page          Address which is on the page to be demapped.
    660  */
    661 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
    662 {
    663         tlb_demap_addr_t da;
    664         page_address_t pg;
    665        
    666         da.value = 0;
    667         pg.address = page;
    668        
    669         da.type = type;
    670         da.context = context_encoding;
    671         da.vpn = pg.vpn;
    672        
    673         /* da.value is the address within the ASI */
    674         asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
    675 
    676         membar();
    677 }
    678 
    679 extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
    680 extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
    681 extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
    682 
    683 extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
    684 
    685 extern void dump_sfsr_and_sfar(void);
    686 
    687 #endif /* !def __ASM__ */
    68844
    68945#endif

  • kernel/arch/sparc64/include/mm/tsb.h

    r1ccafee r0b9ac3c  
    3636#define KERN_sparc64_TSB_H_
    3737
    38 /*
    39  * ITSB abd DTSB will claim 64K of memory, which
    40  * is a nice number considered that it is one of
    41  * the page sizes supported by hardware, which,
    42  * again, is nice because TSBs need to be locked
    43  * in TLBs - only one TLB entry will do.
    44  */
    45 #define TSB_SIZE                        2       /* when changing this, change
    46                                                  * as.c as well */
    47 #define ITSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
    48 #define DTSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
    49 
    50 #define TSB_TAG_TARGET_CONTEXT_SHIFT    48
    51 
    52 #ifndef __ASM__
    53 
    54 #include <arch/mm/tte.h>
    55 #include <arch/mm/mmu.h>
    56 #include <arch/types.h>
    57 
    58 /** TSB Base register. */
    59 typedef union tsb_base_reg {
    60         uint64_t value;
    61         struct {
    62                 uint64_t base : 51;     /**< TSB base address, bits 63:13. */
    63                 unsigned split : 1;     /**< Split vs. common TSB for 8K and 64K
    64                                          * pages. HelenOS uses only 8K pages
    65                                          * for user mappings, so we always set
    66                                          * this to 0.
    67                                          */
    68                 unsigned : 9;
    69                 unsigned size : 3;      /**< TSB size. Number of entries is
    70                                          * 512 * 2^size. */
    71         } __attribute__ ((packed));
    72 } tsb_base_reg_t;
    73 
    74 /** Read ITSB Base register.
    75  *
    76  * @return Content of the ITSB Base register.
    77  */
    78 static inline uint64_t itsb_base_read(void)
    79 {
    80         return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
    81 }
    82 
    83 /** Read DTSB Base register.
    84  *
    85  * @return Content of the DTSB Base register.
    86  */
    87 static inline uint64_t dtsb_base_read(void)
    88 {
    89         return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
    90 }
    91 
    92 /** Write ITSB Base register.
    93  *
    94  * @param v New content of the ITSB Base register.
    95  */
    96 static inline void itsb_base_write(uint64_t v)
    97 {
    98         asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
    99 }
    100 
    101 /** Write DTSB Base register.
    102  *
    103  * @param v New content of the DTSB Base register.
    104  */
    105 static inline void dtsb_base_write(uint64_t v)
    106 {
    107         asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
    108 }
    109 
    110 #if defined (US3)
    111 
    112 /** Write DTSB Primary Extension register.
    113  *
    114  * @param v New content of the DTSB Primary Extension register.
    115  */
    116 static inline void dtsb_primary_extension_write(uint64_t v)
    117 {
    118         asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v);
    119 }
    120 
    121 /** Write DTSB Secondary Extension register.
    122  *
    123  * @param v New content of the DTSB Secondary Extension register.
    124  */
    125 static inline void dtsb_secondary_extension_write(uint64_t v)
    126 {
    127         asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v);
    128 }
    129 
    130 /** Write DTSB Nucleus Extension register.
    131  *
    132  * @param v New content of the DTSB Nucleus Extension register.
    133  */
    134 static inline void dtsb_nucleus_extension_write(uint64_t v)
    135 {
    136         asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v);
    137 }
    138 
    139 /** Write ITSB Primary Extension register.
    140  *
    141  * @param v New content of the ITSB Primary Extension register.
    142  */
    143 static inline void itsb_primary_extension_write(uint64_t v)
    144 {
    145         asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v);
    146 }
    147 
    148 /** Write ITSB Nucleus Extension register.
    149  *
    150  * @param v New content of the ITSB Nucleus Extension register.
    151  */
    152 static inline void itsb_nucleus_extension_write(uint64_t v)
    153 {
    154         asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v);
    155 }
    156 
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/tsb.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/tsb.h>
    15742#endif
    158 
    159 /* Forward declarations. */
    160 struct as;
    161 struct pte;
    162 
    163 extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages);
    164 extern void itsb_pte_copy(struct pte *t, size_t index);
    165 extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro);
    166 
    167 #endif /* !def __ASM__ */
    16843
    16944#endif

  • kernel/arch/sparc64/include/mm/tte.h

    r1ccafee r0b9ac3c  
    3636#define KERN_sparc64_TTE_H_
    3737
    38 #define TTE_G           (1 << 0)
    39 #define TTE_W           (1 << 1)
    40 #define TTE_P           (1 << 2)
    41 #define TTE_E           (1 << 3)
    42 #define TTE_CV          (1 << 4)
    43 #define TTE_CP          (1 << 5)
    44 #define TTE_L           (1 << 6)
    45 
    46 #define TTE_V_SHIFT     63
    47 #define TTE_SIZE_SHIFT  61
    48 
    49 #ifndef __ASM__
    50 
    51 #include <arch/types.h>
    52 
    53 /* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */
    54 #define VA_TAG_PAGE_SHIFT       22
    55 
    56 /** Translation Table Entry - Tag. */
    57 union tte_tag {
    58         uint64_t value;
    59         struct {
    60                 unsigned g : 1;         /**< Global. */
    61                 unsigned : 2;           /**< Reserved. */
    62                 unsigned context : 13;  /**< Context identifier. */
    63                 unsigned : 6;           /**< Reserved. */
    64                 uint64_t va_tag : 42;   /**< Virtual Address Tag, bits 63:22. */
    65         } __attribute__ ((packed));
    66 };
    67 
    68 typedef union tte_tag tte_tag_t;
    69 
    70 /** Translation Table Entry - Data. */
    71 union tte_data {
    72         uint64_t value;
    73         struct {
    74                 unsigned v : 1;         /**< Valid. */
    75                 unsigned size : 2;      /**< Page size of this entry. */
    76                 unsigned nfo : 1;       /**< No-Fault-Only. */
    77                 unsigned ie : 1;        /**< Invert Endianness. */
    78                 unsigned soft2 : 9;     /**< Software defined field. */
    79 #if defined (US)
    80                 unsigned diag : 9;      /**< Diagnostic data. */
    81                 unsigned pfn : 28;      /**< Physical Address bits, bits 40:13. */
    82 #elif defined (US3)
    83                 unsigned : 7;           /**< Reserved. */
    84                 unsigned pfn : 30;      /**< Physical Address bits, bits 42:13 */
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/tte.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/tte.h>
    8542#endif
    86                 unsigned soft : 6;      /**< Software defined field. */
    87                 unsigned l : 1;         /**< Lock. */
    88                 unsigned cp : 1;        /**< Cacheable in physically indexed cache. */
    89                 unsigned cv : 1;        /**< Cacheable in virtually indexed cache. */
    90                 unsigned e : 1;         /**< Side-effect. */
    91                 unsigned p : 1;         /**< Privileged. */
    92                 unsigned w : 1;         /**< Writable. */
    93                 unsigned g : 1;         /**< Global. */
    94         } __attribute__ ((packed));
    95 };
    96 
    97 typedef union tte_data tte_data_t;
    98 
    99 #endif /* !def __ASM__ */
    10043
    10144#endif

  • kernel/arch/sparc64/include/trap/exception.h

    r1ccafee r0b9ac3c  
    3838
    3939#define TT_INSTRUCTION_ACCESS_EXCEPTION         0x08
     40#define TT_INSTRUCTION_ACCESS_MMU_MISS          0x09
    4041#define TT_INSTRUCTION_ACCESS_ERROR             0x0a
     42#define TT_IAE_UNAUTH_ACCESS                    0x0b
     43#define TT_IAE_NFO_PAGE                         0x0c
    4144#define TT_ILLEGAL_INSTRUCTION                  0x10
    4245#define TT_PRIVILEGED_OPCODE                    0x11
    4346#define TT_UNIMPLEMENTED_LDD                    0x12
    4447#define TT_UNIMPLEMENTED_STD                    0x13
     48#define TT_DAE_INVALID_ASI                      0x14
     49#define TT_DAE_PRIVILEGE_VIOLATION              0x15
     50#define TT_DAE_NC_PAGE                          0x16
     51#define TT_DAE_NFO_PAGE                         0x17
    4552#define TT_FP_DISABLED                          0x20
    4653#define TT_FP_EXCEPTION_IEEE_754                0x21
    … …  
    4956#define TT_DIVISION_BY_ZERO                     0x28
    5057#define TT_DATA_ACCESS_EXCEPTION                0x30
     58#define TT_DATA_ACCESS_MMU_MISS                 0x31
    5159#define TT_DATA_ACCESS_ERROR                    0x32
    5260#define TT_MEM_ADDRESS_NOT_ALIGNED              0x34

  • kernel/arch/sparc64/include/trap/interrupt.h

    r1ccafee r0b9ac3c  
    3232/**
    3333 * @file
    34  * @brief This file contains interrupt vector trap handler.
     34 * @brief This file contains level N interrupt and inter-processor interrupt
     35 * trap handler.
    3536 */
    36 
    37 #ifndef KERN_sparc64_TRAP_INTERRUPT_H_
    38 #define KERN_sparc64_TRAP_INTERRUPT_H_
    39 
    40 #include <arch/trap/trap_table.h>
    41 #include <arch/stack.h>
    42 
    43 /* IMAP register bits */
    44 #define IGN_MASK        0x7c0
    45 #define INO_MASK        0x1f
    46 #define IMAP_V_MASK     (1ULL << 31)
    47 
    48 #define IGN_SHIFT       6
    49 
    50 
    51 /* Interrupt ASI registers. */
    52 #define ASI_INTR_W                      0x77
    53 #define ASI_INTR_DISPATCH_STATUS        0x48
    54 #define ASI_INTR_R                      0x7f
    55 #define ASI_INTR_RECEIVE                0x49
    56 
    57 /* VA's used with ASI_INTR_W register. */
    58 #if defined (US)
    59 #define ASI_UDB_INTR_W_DATA_0   0x40
    60 #define ASI_UDB_INTR_W_DATA_1   0x50
    61 #define ASI_UDB_INTR_W_DATA_2   0x60
    62 #elif defined (US3)
    63 #define VA_INTR_W_DATA_0        0x40
    64 #define VA_INTR_W_DATA_1        0x48
    65 #define VA_INTR_W_DATA_2        0x50
    66 #define VA_INTR_W_DATA_3        0x58
    67 #define VA_INTR_W_DATA_4        0x60
    68 #define VA_INTR_W_DATA_5        0x68
    69 #define VA_INTR_W_DATA_6        0x80
    70 #define VA_INTR_W_DATA_7        0x88
    71 #endif
    72 #define VA_INTR_W_DISPATCH      0x70
    73 
    74 /* VA's used with ASI_INTR_R register. */
    75 #if defined(US)
    76 #define ASI_UDB_INTR_R_DATA_0   0x40
    77 #define ASI_UDB_INTR_R_DATA_1   0x50
    78 #define ASI_UDB_INTR_R_DATA_2   0x60
    79 #elif defined (US3)
    80 #define VA_INTR_R_DATA_0        0x40
    81 #define VA_INTR_R_DATA_1        0x48
    82 #define VA_INTR_R_DATA_2        0x50
    83 #define VA_INTR_R_DATA_3        0x58
    84 #define VA_INTR_R_DATA_4        0x60
    85 #define VA_INTR_R_DATA_5        0x68
    86 #define VA_INTR_R_DATA_6        0x80
    87 #define VA_INTR_R_DATA_7        0x88
    88 #endif
    89 
    90 /* Shifts in the Interrupt Vector Dispatch virtual address. */
    91 #define INTR_VEC_DISPATCH_MID_SHIFT     14
    92 
    93 /* Bits in the Interrupt Dispatch Status register. */
    94 #define INTR_DISPATCH_STATUS_NACK       0x2
    95 #define INTR_DISPATCH_STATUS_BUSY       0x1
     37#ifndef KERN_sparc64_INTERRUPT_TRAP_H_
     38#define KERN_sparc64_INTERRUPT_TRAP_H_
    9639
    9740#define TT_INTERRUPT_LEVEL_1                    0x41
    … …  
    11154#define TT_INTERRUPT_LEVEL_15                   0x4f
    11255
    113 #define TT_INTERRUPT_VECTOR_TRAP                0x60
     56#define INTERRUPT_LEVEL_N_HANDLER_SIZE          TRAP_TABLE_ENTRY_SIZE
    11457
    115 #define INTERRUPT_LEVEL_N_HANDLER_SIZE          TRAP_TABLE_ENTRY_SIZE
    116 #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
     58/* IMAP register bits */
     59#define IGN_MASK        0x7c0
     60#define INO_MASK        0x1f
     61#define IMAP_V_MASK     (1ULL << 31)
     62
     63#define IGN_SHIFT       6
     64
    11765
    11866#ifdef __ASM__
    … …  
    12169        PREEMPTIBLE_HANDLER exc_dispatch
    12270.endm
    123 
    124 .macro INTERRUPT_VECTOR_TRAP_HANDLER
    125         PREEMPTIBLE_HANDLER interrupt
    126 .endm
    127 #endif /* __ASM__ */
     71#endif
    12872
    12973#ifndef __ASM__
    … …  
    13478#endif /* !def __ASM__ */
    13579
     80
     81#if defined (SUN4U)
     82#include <arch/trap/sun4u/interrupt.h>
     83#elif defined (SUN4V)
     84#include <arch/trap/sun4v/interrupt.h>
     85#endif
     86
    13687#endif
    13788

  • kernel/arch/sparc64/include/trap/mmu.h

    r1ccafee r0b9ac3c  
    3838#define KERN_sparc64_MMU_TRAP_H_
    3939
    40 #include <arch/stack.h>
    41 #include <arch/regdef.h>
    42 #include <arch/mm/tlb.h>
    43 #include <arch/mm/mmu.h>
    44 #include <arch/mm/tte.h>
    45 #include <arch/trap/regwin.h>
    46 
    47 #ifdef CONFIG_TSB
    48 #include <arch/mm/tsb.h>
     40#if defined (SUN4U)
     41#include <arch/trap/sun4u/mmu.h>
     42#elif defined (SUN4V)
     43#include <arch/trap/sun4v/mmu.h>
    4944#endif
    50 
    51 #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS     0x64
    52 #define TT_FAST_DATA_ACCESS_MMU_MISS            0x68
    53 #define TT_FAST_DATA_ACCESS_PROTECTION          0x6c
    54 
    55 #define FAST_MMU_HANDLER_SIZE                   128
    56 
    57 #ifdef __ASM__
    58 
    59 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    60         /*
    61          * First, try to refill TLB from TSB.
    62          */
    63 #ifdef CONFIG_TSB
    64         ldxa [%g0] ASI_IMMU, %g1                        ! read TSB Tag Target Register
    65         ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2        ! read TSB 8K Pointer
    66         ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
    67         cmp %g1, %g4                                    ! is this the entry we are looking for?
    68         bne,pn %xcc, 0f
    69         nop
    70         stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG            ! copy mapping from ITSB to ITLB
    71         retry
    72 #endif
    73 
    74 0:
    75         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    76         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
    77 .endm
    78 
    79 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
    80         /*
    81          * First, try to refill TLB from TSB.
    82          */
    83 
    84 #ifdef CONFIG_TSB
    85         ldxa [%g0] ASI_DMMU, %g1                        ! read TSB Tag Target Register
    86         srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2     ! is this a kernel miss?
    87         brz,pn %g2, 0f
    88         ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3        ! read TSB 8K Pointer
    89         ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
    90         cmp %g1, %g4                                    ! is this the entry we are looking for?
    91         bne,pn %xcc, 0f
    92         nop
    93         stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG            ! copy mapping from DTSB to DTLB
    94         retry
    95 #endif
    96 
    97         /*
    98          * Second, test if it is the portion of the kernel address space
    99          * which is faulting. If that is the case, immediately create
    100          * identity mapping for that page in DTLB. VPN 0 is excluded from
    101          * this treatment.
    102          *
    103          * Note that branch-delay slots are used in order to save space.
    104          */
    105 0:
    106         sethi %hi(fast_data_access_mmu_miss_data_hi), %g7
    107         wr %g0, ASI_DMMU, %asi
    108         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
    109         set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
    110         andcc %g1, %g2, %g3                             ! get Context
    111         bnz %xcc, 0f                                    ! Context is non-zero
    112         andncc %g1, %g2, %g3                            ! get page address into %g3
    113         bz  %xcc, 0f                                    ! page address is zero
    114         ldx [%g7 + %lo(end_of_identity)], %g4
    115         cmp %g3, %g4
    116         bgeu %xcc, 0f
    117 
    118         ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2
    119         add %g3, %g2, %g2
    120         stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
    121         retry
    122 
    123         /*
    124          * Third, catch and handle special cases when the trap is caused by
    125          * the userspace register window spill or fill handler. In case
    126          * one of these two traps caused this trap, we just lower the trap
    127          * level and service the DTLB miss. In the end, we restart
    128          * the offending SAVE or RESTORE.
    129          */
    130 0:
    131 .if (\tl > 0)
    132         wrpr %g0, 1, %tl
    133 .endif
    134 
    135         /*
    136          * Switch from the MM globals.
    137          */
    138         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    139 
    140         /*
    141          * Read the Tag Access register for the higher-level handler.
    142          * This is necessary to survive nested DTLB misses.
    143          */     
    144         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
    145 
    146         /*
    147          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    148          */
    149         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
    150 .endm
    151 
    152 .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
    153         /*
    154          * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
    155          */
    156 
    157 .if (\tl > 0)
    158         wrpr %g0, 1, %tl
    159 .endif
    160 
    161         /*
    162          * Switch from the MM globals.
    163          */
    164         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    165 
    166         /*
    167          * Read the Tag Access register for the higher-level handler.
    168          * This is necessary to survive nested DTLB misses.
    169          */     
    170         mov VA_DMMU_TAG_ACCESS, %g2
    171         ldxa [%g2] ASI_DMMU, %g2
    172 
    173         /*
    174          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    175          */
    176         PREEMPTIBLE_HANDLER fast_data_access_protection
    177 .endm
    178 
    179 #endif /* __ASM__ */
    18045
    18146#endif

  • kernel/arch/sparc64/include/trap/regwin.h

    r1ccafee r0b9ac3c  
    131131
    132132/*
    133  * Macro used to spill userspace window to userspace window buffer.
    134  * It can be either triggered from preemptible_handler doing SAVE
    135  * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0
    136  * at (TL=0).
    137  */
    138 .macro SPILL_TO_USPACE_WINDOW_BUFFER
    139         stx %l0, [%g7 + L0_OFFSET]     
    140         stx %l1, [%g7 + L1_OFFSET]
    141         stx %l2, [%g7 + L2_OFFSET]
    142         stx %l3, [%g7 + L3_OFFSET]
    143         stx %l4, [%g7 + L4_OFFSET]
    144         stx %l5, [%g7 + L5_OFFSET]
    145         stx %l6, [%g7 + L6_OFFSET]
    146         stx %l7, [%g7 + L7_OFFSET]
    147         stx %i0, [%g7 + I0_OFFSET]
    148         stx %i1, [%g7 + I1_OFFSET]
    149         stx %i2, [%g7 + I2_OFFSET]
    150         stx %i3, [%g7 + I3_OFFSET]
    151         stx %i4, [%g7 + I4_OFFSET]
    152         stx %i5, [%g7 + I5_OFFSET]
    153         stx %i6, [%g7 + I6_OFFSET]
    154         stx %i7, [%g7 + I7_OFFSET]
    155         add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7
    156         saved
    157         retry
    158 .endm
    159 
    160 
    161 /*
    162133 * Macro used by the nucleus and the primary context 0 during normal fills.
    163134 */
    … …  
    232203#endif /* __ASM__ */
    233204
     205#if defined (SUN4U)
     206#include <arch/trap/sun4u/regwin.h>
     207#elif defined (SUN4V)
     208#include <arch/trap/sun4v/regwin.h>
    234209#endif
    235210
     211#endif
     212
    236213/** @}
    237214 */

  • kernel/arch/sparc64/include/trap/trap_table.h

    r1ccafee r0b9ac3c  
    101101.macro PREEMPTIBLE_HANDLER f
    102102        sethi %hi(\f), %g1
    103         ba %xcc, preemptible_handler
     103        b preemptible_handler
    104104        or %g1, %lo(\f), %g1
    105105.endm

  • kernel/arch/sparc64/include/types.h

    r1ccafee r0b9ac3c  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    5555typedef uint64_t unative_t;
    5656typedef int64_t native_t;
     57typedef uint64_t atomic_count_t;
    5758
    5859typedef struct {
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