Index: boot/arch/riscv64/src/asm.S
===================================================================
--- boot/arch/riscv64/src/asm.S	(revision d639eaa7a43293ef2bf56afc045fe76c6e69341c)
+++ boot/arch/riscv64/src/asm.S	(revision 0a78e4fc664e59673629dee0fb20855def1120d4)
@@ -30,4 +30,8 @@
 #include <arch/arch.h>
 #include <arch/mm.h>
+
+#define MCOUNTEREN_CY_MASK  0x00000001
+#define MCOUNTEREN_TM_MASK  0x00000002
+#define MCOUNTEREN_IR_MASK  0x00000004
 
 #define MSTATUS_MPP_MASK        0x00001800
@@ -91,4 +95,7 @@
 
 FUNCTION_BEGIN(jump_to_kernel)
+	/* Enable performance counters access in supervisor mode */
+	csrsi mcounteren, MCOUNTEREN_CY_MASK | MCOUNTEREN_TM_MASK | MCOUNTEREN_IR_MASK
+	
 	/* Setup SV48 paging for supervisor mode */
 	la t0, ptl_0
@@ -108,5 +115,4 @@
 	li t1, ~MSTATUS_MPP_MASK
 	and t0, t0, t1
-	
 	
 	/*
Index: kernel/arch/riscv64/include/arch/cycle.h
===================================================================
--- kernel/arch/riscv64/include/arch/cycle.h	(revision d639eaa7a43293ef2bf56afc045fe76c6e69341c)
+++ kernel/arch/riscv64/include/arch/cycle.h	(revision 0a78e4fc664e59673629dee0fb20855def1120d4)
@@ -40,5 +40,12 @@
 NO_TRACE static inline uint64_t get_cycle(void)
 {
-	return 0;
+	uint64_t cycle;
+	
+	asm volatile (
+		"rdcycle %[cycle]\n"
+		: [cycle] "=r" (cycle)
+	);
+	
+	return cycle;
 }