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 #include <genarch/ofw/ofw_tree.h>
 /** Finds the parent node of all the CPU nodes (nodes named "cpu" or "cmp").
+ *
 …
 /** @}
  */

kernel/arch/sparc64/include/arch/istate_struct.h

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59	59	#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /*< IMMU TSB nucleus extension register /
60	60	#endif
61
62	61
63	62	/* D-MMU ASIs. */

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 typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
 typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 /** TLB Demap Operation Address. */
 …
 #elif defined (US3)
 /** Read IMMU TLB Data Access Register.
+ *
 …
 #endif
 /** Write IMMU TLB Tag Access Register.
+ *
 …
         return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
+}
 /** Write IMMU TLB Data in Register.

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 #define CONS_PUTCHAR            0x61
 /* return codes */
 #define HV_EOK                  0       /**< Successful return */
 …
 #define HV_EBUSY                17      /**< Operation failed as resource is otherwise busy */
 /**
  * Performs a hyperfast hypervisor API call from the assembly language code.
 …
 #define __HYPERCALL_HYPERFAST(sw_trap_number) \
         ta (sw_trap_number);
 #ifndef __ASSEMBLER__

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71	71	#endif /* !def __ASSEMBLER__ */
72	72
73
74	73	#if defined (SUN4U)
75	74	#include <arch/trap/sun4u/interrupt.h>

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40	40	#include <arch/trap/trap_table.h>
41	41	#include <arch/stack.h>
42
43	42
44	43	/* Interrupt ASI registers. */

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114	114	return pci;
115	115	}
116
117	116
118	117	/** Initialize the Psycho PCI controller.

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 #elif defined (US3)
 void smc_coherence(void *a, size_t l)
+{
 …
 #endif  /* defined(US3) */

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175	175	}
176	176
177
178	177	/*
179	178	* Deliver an IPI to the specified processors (except the current one).

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 #define PROP_STR        0x73    /**< Node property with a string value */
 #define PROP_DATA       0x64    /**< Node property with a block of data */
 /** machine description header */
 …
     __attribute__((aligned(16)));
 /** returns pointer to the element at the given index */
 static md_element_t *get_element(element_idx_t idx)

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