Changeset 0867321 in mainline for kernel/arch/ppc32/src

Timestamp:

2009-02-02T18:06:15Z (17 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

cdda403

Parents:

7b187ef

Message:

very experimental TLB refill for ppc32

Location:

kernel/arch/ppc32/src

Files:

• exception.S (modified) (3 diffs)
• mm/tlb.c (modified) (3 diffs)

kernel/arch/ppc32/src/exception.S

@@ -209 +209 @@
 .global exc_syscall
 exc_syscall:
-        CONTEXT_STORE   
+        CONTEXT_STORE
         
         b jump_to_kernel_syscall
@@ -220 +220 @@
         li r3, 12
         b jump_to_kernel
+
+.org 0x1000
+.global exc_itlb_miss
+exc_itlb_miss:
+        CONTEXT_STORE
+        
+        b tlb_miss
+
+.org 0x1100
+.global exc_dtlb_miss_load
+exc_dtlb_miss_load:
+        CONTEXT_STORE
+        
+        b tlb_miss
+
+.org 0x1200
+.global exc_dtlb_miss_store
+exc_dtlb_miss_store:
+        CONTEXT_STORE
+        
+        b tlb_miss
 
 .org 0x4000
@@ -245 +266 @@
         li r3, 3
         b jump_to_kernel
+
+tlb_miss:
+        li r3, 16
+        mfspr r4, tlbmiss
+        mfspr r5, ptehi
+        mfspr r6, ptelo
+        mr r7, sp
+        addi r7, r7, 20
+        
+        bl tlb_refill_real
+        b iret_real
 
 jump_to_kernel:

kernel/arch/ppc32/src/mm/tlb.c

@@ -228 +228 @@
 
 
-/** Process Instruction/Data Storage Interrupt
- *
- * @param n             Interrupt vector number.
- * @param istate        Interrupted register context.
+/** Process Instruction/Data Storage Exception
+ *
+ * @param n      Exception vector number.
+ * @param istate Interrupted register context.
  *
  */
@@ -288 +288 @@
 
 
-/** Process Instruction/Data Storage Interrupt in Real Mode
- *
- * @param n             Interrupt vector number.
- * @param istate        Interrupted register context.
+/** Process Instruction/Data Storage Exception in Real Mode
+ *
+ * @param n      Exception vector number.
+ * @param istate Interrupted register context.
  *
  */
@@ -406 +406 @@
         
         return true;
+}
+
+
+/** Process ITLB/DTLB Miss Exception in Real Mode
+ *
+ *
+ */
+void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate)
+{
+        uint32_t badvaddr = tlbmiss & 0xfffffffc;
+        
+        uint32_t physmem;
+        asm volatile (
+                "mfsprg3 %0\n"
+                : "=r" (physmem)
+        );
+        
+        if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
+                return; // FIXME
+        
+        ptelo.rpn = KA2PA(badvaddr) >> 12;
+        ptelo.wimg = 0;
+        ptelo.pp = 2; // FIXME
+        
+        uint32_t index = 0;
+        asm volatile (
+                "mtspr 981, %0\n"
+                "mtspr 982, %1\n"
+                "tlbld %2\n"
+                "tlbli %2\n"
+                : "=r" (index)
+                : "r" (ptehi),
+                  "r" (ptelo)
+        );
 }