Index: uspace/lib/libc/arch/mips32/src/entry.s
===================================================================
--- uspace/lib/libc/arch/mips32/src/entry.s	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ uspace/lib/libc/arch/mips32/src/entry.s	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
@@ -0,0 +1,89 @@
+#
+# Copyright (c) 2005 Martin Decky
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+.text
+.section .init, "ax"
+.global __entry
+.global __entry_driver
+.set noreorder
+.option pic2
+
+## User-space task entry point
+#
+#
+.ent __entry
+__entry:
+	.frame $sp, 32, $31
+	.cpload $25
+	
+	
+	# Mips o32 may store its arguments on stack, make space (16 bytes),
+	# so that it could work with -O0
+	# Make space additional 16 bytes for the stack frame
+
+	addiu $sp, -32
+	.cprestore 16   # Allow PIC code
+	
+	jal __main
+	nop
+	
+	jal __io_init
+	nop
+	
+	jal main
+	nop
+	
+	jal __exit
+	nop
+.end
+
+.ent __entry_driver
+__entry_driver:
+	.frame $sp, 32, $31
+	.cpload $25
+	
+	
+	# Mips o32 may store its arguments on stack, make space (16 bytes),
+	# so that it could work with -O0
+	# Make space additional 16 bytes for the stack frame
+
+	addiu $sp, -32
+	.cprestore 16   # Allow PIC code
+	
+	jal __main
+	nop
+	
+	jal main
+	nop
+	
+	jal __exit
+	nop
+.end
+# Alignment of output section data to 0x4000
+.section .data
+.align 14
Index: uspace/lib/libc/arch/mips32/src/psthread.S
===================================================================
--- uspace/lib/libc/arch/mips32/src/psthread.S	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ uspace/lib/libc/arch/mips32/src/psthread.S	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
@@ -0,0 +1,161 @@
+#
+# Copyright (c) 2003-2004 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+.text
+
+.set noat
+.set noreorder
+
+
+#include <arch/asm/regname.h>
+#include <libarch/context_offset.h>
+	
+.global context_save
+.global context_restore
+	
+.macro CONTEXT_STORE r
+	sw $s0,OFFSET_S0(\r)
+	sw $s1,OFFSET_S1(\r)
+	sw $s2,OFFSET_S2(\r)
+	sw $s3,OFFSET_S3(\r)
+	sw $s4,OFFSET_S4(\r)
+	sw $s5,OFFSET_S5(\r)
+	sw $s6,OFFSET_S6(\r)
+	sw $s7,OFFSET_S7(\r)
+	sw $s8,OFFSET_S8(\r)
+	sw $gp,OFFSET_GP(\r)
+	sw $k1,OFFSET_TLS(\r)
+
+#ifdef CONFIG_MIPS_FPU	
+	mfc1 $t0,$20
+	sw $t0, OFFSET_F20(\r)
+
+	mfc1 $t0,$21
+	sw $t0, OFFSET_F21(\r)
+
+	mfc1 $t0,$22
+	sw $t0, OFFSET_F22(\r)
+
+	mfc1 $t0,$23
+	sw $t0, OFFSET_F23(\r)
+
+	mfc1 $t0,$24
+	sw $t0, OFFSET_F24(\r)
+
+	mfc1 $t0,$25
+	sw $t0, OFFSET_F25(\r)
+
+	mfc1 $t0,$26
+	sw $t0, OFFSET_F26(\r)
+
+	mfc1 $t0,$27
+	sw $t0, OFFSET_F27(\r)
+
+	mfc1 $t0,$28
+	sw $t0, OFFSET_F28(\r)
+
+	mfc1 $t0,$29
+	sw $t0, OFFSET_F29(\r)
+	
+	mfc1 $t0,$30
+	sw $t0, OFFSET_F30(\r)
+#endif	
+		
+	sw $ra,OFFSET_PC(\r)
+	sw $sp,OFFSET_SP(\r)
+.endm
+
+.macro CONTEXT_LOAD r
+	lw $s0,OFFSET_S0(\r)
+	lw $s1,OFFSET_S1(\r)
+	lw $s2,OFFSET_S2(\r)
+	lw $s3,OFFSET_S3(\r)
+	lw $s4,OFFSET_S4(\r)
+	lw $s5,OFFSET_S5(\r)
+	lw $s6,OFFSET_S6(\r)
+	lw $s7,OFFSET_S7(\r)
+	lw $s8,OFFSET_S8(\r)
+	lw $gp,OFFSET_GP(\r)
+	lw $k1,OFFSET_TLS(\r)
+
+#ifdef CONFIG_MIPS_FPU	
+	lw $t0, OFFSET_F20(\r)
+	mtc1 $t0,$20
+
+	lw $t0, OFFSET_F21(\r)
+	mtc1 $t0,$21
+
+	lw $t0, OFFSET_F22(\r)
+	mtc1 $t0,$22
+
+	lw $t0, OFFSET_F23(\r)
+	mtc1 $t0,$23
+
+	lw $t0, OFFSET_F24(\r)
+	mtc1 $t0,$24
+
+	lw $t0, OFFSET_F25(\r)
+	mtc1 $t0,$25
+
+	lw $t0, OFFSET_F26(\r)
+	mtc1 $t0,$26
+
+	lw $t0, OFFSET_F27(\r)
+	mtc1 $t0,$27
+
+	lw $t0, OFFSET_F28(\r)
+	mtc1 $t0,$28
+
+	lw $t0, OFFSET_F29(\r)
+	mtc1 $t0,$29
+
+	lw $t0, OFFSET_F30(\r)
+	mtc1 $t0,$30
+#endif	
+		
+	lw $ra,OFFSET_PC(\r)
+	lw $sp,OFFSET_SP(\r)
+.endm
+	
+context_save:
+	CONTEXT_STORE $a0
+
+	# context_save returns 1
+	j $ra
+	li $v0, 1	
+	
+context_restore:
+	CONTEXT_LOAD $a0
+
+	# Just for the jump into first function, but one instruction
+	# should not bother us
+	move $t9, $ra	
+	# context_restore returns 0
+	j $ra
+	xor $v0, $v0	
+
Index: uspace/lib/libc/arch/mips32/src/syscall.c
===================================================================
--- uspace/lib/libc/arch/mips32/src/syscall.c	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ uspace/lib/libc/arch/mips32/src/syscall.c	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2005 Martin Decky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /** @addtogroup libcmips32
+ * @{
+ */
+/** @file
+  * @ingroup libcmips32eb	
+ */
+
+#include <libc.h>
+
+sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, 
+		   const sysarg_t p3, const sysarg_t p4,
+		   const syscall_t id)
+{
+	register sysarg_t __mips_reg_a0 asm("$4") = p1;
+	register sysarg_t __mips_reg_a1 asm("$5") = p2;
+	register sysarg_t __mips_reg_a2 asm("$6") = p3;
+	register sysarg_t __mips_reg_a3 asm("$7") = p4;
+	register sysarg_t __mips_reg_v0 asm("$2") = id;
+	
+	asm volatile (
+		"syscall\n"
+		: "=r" (__mips_reg_v0)
+		: "r" (__mips_reg_a0),
+		  "r" (__mips_reg_a1),
+		  "r" (__mips_reg_a2),
+		  "r" (__mips_reg_a3),
+		  "r" (__mips_reg_v0)
+		: "%ra" /* We are a function call, although C does not 
+			 * know it */
+	);
+	
+	return __mips_reg_v0;
+}
+
+ /** @}
+ */
+
Index: uspace/lib/libc/arch/mips32/src/thread.c
===================================================================
--- uspace/lib/libc/arch/mips32/src/thread.c	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ uspace/lib/libc/arch/mips32/src/thread.c	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2006 Ondrej Palkovsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup libcmips32	
+ * @{
+ */
+/** @file
+ * @ingroup libcmips32eb	
+ */
+
+#include <thread.h>
+#include <malloc.h>
+
+/** Allocate TLS & TCB for initial module threads
+ *
+ * @param data (out) Start of TLS section
+ * @param size Size of tdata+tbss section
+ * @return pointer to tcb_t structure
+ */
+tcb_t * __alloc_tls(void **data, size_t size)
+{
+	tcb_t *result;
+
+	result = malloc(sizeof(tcb_t) + size);
+	*data = ((void *)result) + sizeof(tcb_t);
+	return result;
+}
+
+void __free_tls_arch(tcb_t *tcb, size_t size)
+{
+	free(tcb);
+}
+
+/** @}
+ */
Index: uspace/lib/libc/arch/mips32/src/thread_entry.s
===================================================================
--- uspace/lib/libc/arch/mips32/src/thread_entry.s	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ uspace/lib/libc/arch/mips32/src/thread_entry.s	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2006 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+.text
+	
+.set noat
+.set noreorder
+.option pic2
+	
+.globl __thread_entry
+
+## User-space thread entry point for all but the first threads.
+#
+#
+.ent __thread_entry
+__thread_entry:
+	.frame $sp, 32, $31
+	.cpload $25
+
+	#
+	# v0 contains address of uarg.
+	#
+	add $4, $2, 0
+	# Mips o32 may store its arguments on stack, make space
+	addiu $sp, -32
+	.cprestore 16
+	
+	jal __thread_main
+	nop
+		
+	#
+	# Not reached.
+	#
+.end __thread_entry
