source: mainline/uspace/srv/net/netif/dp8390/dp8390.h@ 5297fe8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5297fe8 was aa8267c, checked in by Jakub Jermar <jakub@…>, 15 years ago

The MINIX 3 dp8390 has existential problems with 64-bits.
  • Property mode set to 100644
File size: 15.9 KB
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1/*
2 * Copyright (c) 1987,1997, 2006, Vrije Universiteit, Amsterdam, The Netherlands All rights reserved. Redistribution and use of the MINIX 3 operating system in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
3 *
4 * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
5 * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
6 * * Neither the name of the Vrije Universiteit nor the names of the software authors or contributors may be used to endorse or promote products derived from this software without specific prior written permission.
7 * * Any deviations from these conditions require written permission from the copyright holder in advance
8 *
9 *
10 * Disclaimer
11 *
12 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS, AUTHORS, AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR
13 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
14 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ANY AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
18 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
19 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * Changes:
24 * 2009 ported to HelenOS, Lukas Mejdrech
25 */
26
27/** @addtogroup dp8390
28 * @{
29 */
30
31/** @file
32 * DP8390 network interface definitions.
33 */
34
35#ifndef __NET_NETIF_DP8390_H__
36#define __NET_NETIF_DP8390_H__
37
38#include "../../structures/packet/packet.h"
39
40#include "dp8390_port.h"
41#include "local.h"
42
43/** Input/output size.
44 */
45#define DP8390_IO_SIZE 0x01f
46
47/*
48dp8390.h
49
50Created: before Dec 28, 1992 by Philip Homburg
51*/
52
53/* National Semiconductor DP8390 Network Interface Controller. */
54
55 /* Page 0, for reading ------------- */
56#define DP_CR 0x0 /* Read side of Command Register */
57#define DP_CLDA0 0x1 /* Current Local Dma Address 0 */
58#define DP_CLDA1 0x2 /* Current Local Dma Address 1 */
59#define DP_BNRY 0x3 /* Boundary Pointer */
60#define DP_TSR 0x4 /* Transmit Status Register */
61#define DP_NCR 0x5 /* Number of Collisions Register */
62#define DP_FIFO 0x6 /* Fifo ?? */
63#define DP_ISR 0x7 /* Interrupt Status Register */
64#define DP_CRDA0 0x8 /* Current Remote Dma Address 0 */
65#define DP_CRDA1 0x9 /* Current Remote Dma Address 1 */
66#define DP_DUM1 0xA /* unused */
67#define DP_DUM2 0xB /* unused */
68#define DP_RSR 0xC /* Receive Status Register */
69#define DP_CNTR0 0xD /* Tally Counter 0 */
70#define DP_CNTR1 0xE /* Tally Counter 1 */
71#define DP_CNTR2 0xF /* Tally Counter 2 */
72
73 /* Page 0, for writing ------------- */
74#define DP_CR 0x0 /* Write side of Command Register */
75#define DP_PSTART 0x1 /* Page Start Register */
76#define DP_PSTOP 0x2 /* Page Stop Register */
77#define DP_BNRY 0x3 /* Boundary Pointer */
78#define DP_TPSR 0x4 /* Transmit Page Start Register */
79#define DP_TBCR0 0x5 /* Transmit Byte Count Register 0 */
80#define DP_TBCR1 0x6 /* Transmit Byte Count Register 1 */
81#define DP_ISR 0x7 /* Interrupt Status Register */
82#define DP_RSAR0 0x8 /* Remote Start Address Register 0 */
83#define DP_RSAR1 0x9 /* Remote Start Address Register 1 */
84#define DP_RBCR0 0xA /* Remote Byte Count Register 0 */
85#define DP_RBCR1 0xB /* Remote Byte Count Register 1 */
86#define DP_RCR 0xC /* Receive Configuration Register */
87#define DP_TCR 0xD /* Transmit Configuration Register */
88#define DP_DCR 0xE /* Data Configuration Register */
89#define DP_IMR 0xF /* Interrupt Mask Register */
90
91 /* Page 1, read/write -------------- */
92#define DP_CR 0x0 /* Command Register */
93#define DP_PAR0 0x1 /* Physical Address Register 0 */
94#define DP_PAR1 0x2 /* Physical Address Register 1 */
95#define DP_PAR2 0x3 /* Physical Address Register 2 */
96#define DP_PAR3 0x4 /* Physical Address Register 3 */
97#define DP_PAR4 0x5 /* Physical Address Register 4 */
98#define DP_PAR5 0x6 /* Physical Address Register 5 */
99#define DP_CURR 0x7 /* Current Page Register */
100#define DP_MAR0 0x8 /* Multicast Address Register 0 */
101#define DP_MAR1 0x9 /* Multicast Address Register 1 */
102#define DP_MAR2 0xA /* Multicast Address Register 2 */
103#define DP_MAR3 0xB /* Multicast Address Register 3 */
104#define DP_MAR4 0xC /* Multicast Address Register 4 */
105#define DP_MAR5 0xD /* Multicast Address Register 5 */
106#define DP_MAR6 0xE /* Multicast Address Register 6 */
107#define DP_MAR7 0xF /* Multicast Address Register 7 */
108
109/* Bits in dp_cr */
110#define CR_STP 0x01 /* Stop: software reset */
111#define CR_STA 0x02 /* Start: activate NIC */
112#define CR_TXP 0x04 /* Transmit Packet */
113#define CR_DMA 0x38 /* Mask for DMA control */
114#define CR_DM_NOP 0x00 /* DMA: No Operation */
115#define CR_DM_RR 0x08 /* DMA: Remote Read */
116#define CR_DM_RW 0x10 /* DMA: Remote Write */
117#define CR_DM_SP 0x18 /* DMA: Send Packet */
118#define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */
119#define CR_PS 0xC0 /* Mask for Page Select */
120#define CR_PS_P0 0x00 /* Register Page 0 */
121#define CR_PS_P1 0x40 /* Register Page 1 */
122#define CR_PS_P2 0x80 /* Register Page 2 */
123#define CR_PS_T1 0xC0 /* Test Mode Register Map */
124
125/* Bits in dp_isr */
126#define ISR_PRX 0x01 /* Packet Received with no errors */
127#define ISR_PTX 0x02 /* Packet Transmitted with no errors */
128#define ISR_RXE 0x04 /* Receive Error */
129#define ISR_TXE 0x08 /* Transmit Error */
130#define ISR_OVW 0x10 /* Overwrite Warning */
131#define ISR_CNT 0x20 /* Counter Overflow */
132#define ISR_RDC 0x40 /* Remote DMA Complete */
133#define ISR_RST 0x80 /* Reset Status */
134
135/* Bits in dp_imr */
136#define IMR_PRXE 0x01 /* Packet Received iEnable */
137#define IMR_PTXE 0x02 /* Packet Transmitted iEnable */
138#define IMR_RXEE 0x04 /* Receive Error iEnable */
139#define IMR_TXEE 0x08 /* Transmit Error iEnable */
140#define IMR_OVWE 0x10 /* Overwrite Warning iEnable */
141#define IMR_CNTE 0x20 /* Counter Overflow iEnable */
142#define IMR_RDCE 0x40 /* DMA Complete iEnable */
143
144/* Bits in dp_dcr */
145#define DCR_WTS 0x01 /* Word Transfer Select */
146#define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */
147#define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */
148#define DCR_BOS 0x02 /* Byte Order Select */
149#define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */
150#define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */
151#define DCR_LAS 0x04 /* Long Address Select */
152#define DCR_BMS 0x08 /* Burst Mode Select
153 * Called Loopback Select (LS) in
154 * later manuals. Should be set. */
155#define DCR_AR 0x10 /* Autoinitialize Remote */
156#define DCR_FTS 0x60 /* Fifo Threshold Select */
157#define DCR_2BYTES 0x00 /* 2 bytes */
158#define DCR_4BYTES 0x40 /* 4 bytes */
159#define DCR_8BYTES 0x20 /* 8 bytes */
160#define DCR_12BYTES 0x60 /* 12 bytes */
161
162/* Bits in dp_tcr */
163#define TCR_CRC 0x01 /* Inhibit CRC */
164#define TCR_ELC 0x06 /* Encoded Loopback Control */
165#define TCR_NORMAL 0x00 /* ELC: Normal Operation */
166#define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */
167#define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */
168#define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */
169#define TCR_ATD 0x08 /* Auto Transmit Disable */
170#define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */
171
172/* Bits in dp_tsr */
173#define TSR_PTX 0x01 /* Packet Transmitted (without error)*/
174#define TSR_DFR 0x02 /* Transmit Deferred, reserved in
175 * later manuals. */
176#define TSR_COL 0x04 /* Transmit Collided */
177#define TSR_ABT 0x08 /* Transmit Aborted */
178#define TSR_CRS 0x10 /* Carrier Sense Lost */
179#define TSR_FU 0x20 /* FIFO Underrun */
180#define TSR_CDH 0x40 /* CD Heartbeat */
181#define TSR_OWC 0x80 /* Out of Window Collision */
182
183/* Bits in tp_rcr */
184#define RCR_SEP 0x01 /* Save Errored Packets */
185#define RCR_AR 0x02 /* Accept Runt Packets */
186#define RCR_AB 0x04 /* Accept Broadcast */
187#define RCR_AM 0x08 /* Accept Multicast */
188#define RCR_PRO 0x10 /* Physical Promiscuous */
189#define RCR_MON 0x20 /* Monitor Mode */
190
191/* Bits in dp_rsr */
192#define RSR_PRX 0x01 /* Packet Received Intact */
193#define RSR_CRC 0x02 /* CRC Error */
194#define RSR_FAE 0x04 /* Frame Alignment Error */
195#define RSR_FO 0x08 /* FIFO Overrun */
196#define RSR_MPA 0x10 /* Missed Packet */
197#define RSR_PHY 0x20 /* Multicast Address Match */
198#define RSR_DIS 0x40 /* Receiver Disabled */
199#define RSR_DFR 0x80 /* In later manuals: Deferring */
200
201/** Type definition of the receive header.
202 */
203typedef struct dp_rcvhdr
204{
205 /** Copy of rsr.
206 */
207 u8_t dr_status;
208 /** Pointer to next packet.
209 */
210 u8_t dr_next;
211 /** Receive Byte Count Low.
212 */
213 u8_t dr_rbcl;
214 /** Receive Byte Count High.
215 */
216 u8_t dr_rbch;
217} dp_rcvhdr_t;
218
219/** Page size.
220 */
221#define DP_PAGESIZE 256
222
223/* Some macros to simplify accessing the dp8390 */
224/** Reads 1 byte from the zero page register.
225 * @param[in] dep The network interface structure.
226 * @param[in] reg The register offset.
227 * @returns The read value.
228 */
229#define inb_reg0(dep, reg) (inb(dep->de_dp8390_port+reg))
230
231/** Writes 1 byte zero page register.
232 * @param[in] dep The network interface structure.
233 * @param[in] reg The register offset.
234 * @param[in] data The value to be written.
235 */
236#define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port+reg, data))
237
238/** Reads 1 byte from the first page register.
239 * @param[in] dep The network interface structure.
240 * @param[in] reg The register offset.
241 * @returns The read value.
242 */
243#define inb_reg1(dep, reg) (inb(dep->de_dp8390_port+reg))
244
245/** Writes 1 byte first page register.
246 * @param[in] dep The network interface structure.
247 * @param[in] reg The register offset.
248 * @param[in] data The value to be written.
249 */
250#define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port+reg, data))
251
252/* Software interface to the dp8390 driver */
253
254struct dpeth;
255struct iovec_dat;
256//struct iovec_dat_s;
257_PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep) );
258_PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep) );
259_PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep,
260 struct iovec_dat *iovp, vir_bytes offset,
261 int nic_addr, vir_bytes count) );
262//_PROTOTYPE( typedef void (*dp_user2nicf_s_t), (struct dpeth *dep,
263// struct iovec_dat_s *iovp, vir_bytes offset,
264// int nic_addr, vir_bytes count) );
265_PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep,
266 int nic_addr, struct iovec_dat *iovp,
267 vir_bytes offset, vir_bytes count) );
268//_PROTOTYPE( typedef void (*dp_nic2userf_s_t), (struct dpeth *dep,
269// int nic_addr, struct iovec_dat_s *iovp,
270// vir_bytes offset, vir_bytes count) );
271//#if 0
272//_PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep,
273// int page, struct dp_rcvhdr *h, u16_t *eth_type) );
274//#endif
275_PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep,
276 int page, size_t offset, size_t size, void *dst) );
277
278/* iovectors are handled IOVEC_NR entries at a time. */
279//#define IOVEC_NR 16
280// no vectors allowed
281#define IOVEC_NR 1
282
283/*
284typedef int irq_hook_t;
285*/
286typedef struct iovec_dat
287{
288 iovec_t iod_iovec[IOVEC_NR];
289 int iod_iovec_s;
290 // no direct process access
291 int iod_proc_nr;
292 vir_bytes iod_iovec_addr;
293} iovec_dat_t;
294/*
295typedef struct iovec_dat_s
296{
297 iovec_s_t iod_iovec[IOVEC_NR];
298 int iod_iovec_s;
299 int iod_proc_nr;
300 cp_grant_id_t iod_grant;
301 vir_bytes iod_iovec_offset;
302} iovec_dat_s_t;
303*/
304#define SENDQ_NR 1 /* Maximum size of the send queue */
305#define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */
306
307/** Maximum number of waiting packets to be sent or received.
308 */
309#define MAX_PACKETS 4
310
311typedef struct dpeth
312{
313 /** Outgoing packets queue.
314 */
315 packet_t packet_queue;
316 /** Outgoing packets count.
317 */
318 int packet_count;
319
320 /** Received packets queue.
321 */
322 packet_t received_queue;
323 /** Received packets count.
324 */
325 int received_count;
326
327 /* The de_base_port field is the starting point of the probe.
328 * The conf routine also fills de_linmem and de_irq. If the probe
329 * routine knows the irq and/or memory address because they are
330 * hardwired in the board, the probe should modify these fields.
331 * Futhermore, the probe routine should also fill in de_initf and
332 * de_stopf fields with the appropriate function pointers and set
333 * de_prog_IO iff programmed I/O is to be used.
334 */
335 port_t de_base_port;
336 phys_bytes de_linmem;
337 char *de_locmem;
338 int de_irq;
339 int de_int_pending;
340// irq_hook_t de_hook;
341 dp_initf_t de_initf;
342 dp_stopf_t de_stopf;
343 int de_prog_IO;
344 char de_name[sizeof("dp8390#n")];
345
346 /* The initf function fills the following fields. Only cards that do
347 * programmed I/O fill in the de_pata_port field.
348 * In addition, the init routine has to fill in the sendq data
349 * structures.
350 */
351 ether_addr_t de_address;
352 port_t de_dp8390_port;
353 port_t de_data_port;
354 int de_16bit;
355 long de_ramsize;
356 int de_offset_page;
357 int de_startpage;
358 int de_stoppage;
359
360 /* should be here - read even for ne2k isa init... */
361 char de_pci; /* TRUE iff PCI device */
362
363#if ENABLE_PCI
364 /* PCI config */
365// char de_pci; /* TRUE iff PCI device */
366// u8_t de_pcibus;
367// u8_t de_pcidev;
368// u8_t de_pcifunc;
369#endif
370
371 /* Do it yourself send queue */
372 struct sendq
373 {
374 int sq_filled; /* this buffer contains a packet */
375 int sq_size; /* with this size */
376 int sq_sendpage; /* starting page of the buffer */
377 } de_sendq[SENDQ_NR];
378 int de_sendq_nr;
379 int de_sendq_head; /* Enqueue at the head */
380 int de_sendq_tail; /* Dequeue at the tail */
381
382 /* Fields for internal use by the dp8390 driver. */
383 int de_flags;
384 int de_mode;
385 eth_stat_t de_stat;
386 iovec_dat_t de_read_iovec;
387// iovec_dat_s_t de_read_iovec_s;
388// int de_safecopy_read;
389 iovec_dat_t de_write_iovec;
390// iovec_dat_s_t de_write_iovec_s;
391 iovec_dat_t de_tmp_iovec;
392// iovec_dat_s_t de_tmp_iovec_s;
393 vir_bytes de_read_s;
394// int de_client;
395// message de_sendmsg;
396 dp_user2nicf_t de_user2nicf;
397// dp_user2nicf_s_t de_user2nicf_s;
398 dp_nic2userf_t de_nic2userf;
399// dp_nic2userf_s_t de_nic2userf_s;
400 dp_getblock_t de_getblockf;
401} dpeth_t;
402
403#define DEI_DEFAULT 0x8000
404
405#define DEF_EMPTY 0x000
406#define DEF_PACK_SEND 0x001
407#define DEF_PACK_RECV 0x002
408#define DEF_SEND_AVAIL 0x004
409#define DEF_READING 0x010
410#define DEF_PROMISC 0x040
411#define DEF_MULTI 0x080
412#define DEF_BROAD 0x100
413#define DEF_ENABLED 0x200
414#define DEF_STOPPED 0x400
415
416#define DEM_DISABLED 0x0
417#define DEM_SINK 0x1
418#define DEM_ENABLED 0x2
419
420//#if !__minix_vmd
421#define debug 1 /* Standard Minix lacks debug variable */
422//#endif
423
424/*
425 * $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $
426 */
427
428#endif
429
430/** @}
431 */
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