source: mainline/uspace/srv/hw/netif/ne2000/dp8390.h@ d0dd7b5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d0dd7b5 was b72efe8, checked in by Jiri Svoboda <jiri@…>, 14 years ago

Separate list_t typedef from link_t (user-space part).

  • list_t represents lists
  • Use list_first(), list_last(), list_empty() where appropriate
  • Use list_foreach() where possible
  • assert_link_not_used()
  • usb_hid_report_path_free() shall not unlink the path, caller must do it
  • Property mode set to 100644
File size: 9.8 KB
Line 
1/*
2 * Copyright (c) 2009 Lukas Mejdrech
3 * Copyright (c) 2011 Martin Decky
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * This code is based upon the NE2000 driver for MINIX,
32 * distributed according to a BSD-style license.
33 *
34 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
35 * Copyright (c) 1992, 1994 Philip Homburg
36 * Copyright (c) 1996 G. Falzoni
37 *
38 */
39
40/** @addtogroup ne2000
41 * @{
42 */
43
44/** @file
45 * DP8390 network interface definitions.
46 */
47
48#ifndef __NET_NETIF_DP8390_H__
49#define __NET_NETIF_DP8390_H__
50
51#include <fibril_synch.h>
52#include <adt/list.h>
53#include <net/packet.h>
54#include <netif_skel.h>
55
56/** Module name */
57#define NAME "ne2000"
58
59/** Input/output size */
60#define NE2K_IO_SIZE 0x0020
61
62/** Ethernet address length */
63#define ETH_ADDR 6
64
65/* National Semiconductor DP8390 Network Interface Controller. */
66
67/** Page 0, for reading */
68#define DP_CR 0x00 /**< Command Register */
69#define DP_CLDA0 0x01 /**< Current Local DMA Address 0 */
70#define DP_CLDA1 0x02 /**< Current Local DMA Address 1 */
71#define DP_BNRY 0x03 /**< Boundary Pointer */
72#define DP_TSR 0x04 /**< Transmit Status Register */
73#define DP_NCR 0x05 /**< Number of Collisions Register */
74#define DP_FIFO 0x06 /**< FIFO */
75#define DP_ISR 0x07 /**< Interrupt Status Register */
76#define DP_CRDA0 0x08 /**< Current Remote DMA Address 0 */
77#define DP_CRDA1 0x09 /**< Current Remote DMA Address 1 */
78#define DP_RSR 0x0c /**< Receive Status Register */
79#define DP_CNTR0 0x0d /**< Tally Counter 0 */
80#define DP_CNTR1 0x0e /**< Tally Counter 1 */
81#define DP_CNTR2 0x0f /**< Tally Counter 2 */
82
83/** Page 0, for writing */
84#define DP_PSTART 0x01 /**< Page Start Register*/
85#define DP_PSTOP 0x02 /**< Page Stop Register */
86#define DP_TPSR 0x04 /**< Transmit Page Start Register */
87#define DP_TBCR0 0x05 /**< Transmit Byte Count Register 0 */
88#define DP_TBCR1 0x06 /**< Transmit Byte Count Register 1 */
89#define DP_RSAR0 0x08 /**< Remote Start Address Register 0 */
90#define DP_RSAR1 0x09 /**< Remote Start Address Register 1 */
91#define DP_RBCR0 0x0a /**< Remote Byte Count Register 0 */
92#define DP_RBCR1 0x0b /**< Remote Byte Count Register 1 */
93#define DP_RCR 0x0c /**< Receive Configuration Register */
94#define DP_TCR 0x0d /**< Transmit Configuration Register */
95#define DP_DCR 0x0e /**< Data Configuration Register */
96#define DP_IMR 0x0f /**< Interrupt Mask Register */
97
98/** Page 1, read/write */
99#define DP_PAR0 0x01 /**< Physical Address Register 0 */
100#define DP_PAR1 0x02 /**< Physical Address Register 1 */
101#define DP_PAR2 0x03 /**< Physical Address Register 2 */
102#define DP_PAR3 0x04 /**< Physical Address Register 3 */
103#define DP_PAR4 0x05 /**< Physical Address Register 4 */
104#define DP_PAR5 0x06 /**< Physical Address Register 5 */
105#define DP_CURR 0x07 /**< Current Page Register */
106#define DP_MAR0 0x08 /**< Multicast Address Register 0 */
107#define DP_MAR1 0x09 /**< Multicast Address Register 1 */
108#define DP_MAR2 0x0a /**< Multicast Address Register 2 */
109#define DP_MAR3 0x0b /**< Multicast Address Register 3 */
110#define DP_MAR4 0x0c /**< Multicast Address Register 4 */
111#define DP_MAR5 0x0d /**< Multicast Address Register 5 */
112#define DP_MAR6 0x0e /**< Multicast Address Register 6 */
113#define DP_MAR7 0x0f /**< Multicast Address Register 7 */
114
115/* Bits in Command Register */
116#define CR_STP 0x01 /**< Stop (software reset) */
117#define CR_STA 0x02 /**< Start (activate NIC) */
118#define CR_TXP 0x04 /**< Transmit Packet */
119#define CR_DMA 0x38 /**< Mask for DMA control */
120#define CR_DM_NOP 0x00 /**< DMA: No Operation */
121#define CR_DM_RR 0x08 /**< DMA: Remote Read */
122#define CR_DM_RW 0x10 /**< DMA: Remote Write */
123#define CR_DM_SP 0x18 /**< DMA: Send Packet */
124#define CR_DM_ABORT 0x20 /**< DMA: Abort Remote DMA Operation */
125#define CR_PS 0xc0 /**< Mask for Page Select */
126#define CR_PS_P0 0x00 /**< Register Page 0 */
127#define CR_PS_P1 0x40 /**< Register Page 1 */
128#define CR_PS_P2 0x80 /**< Register Page 2 */
129#define CR_PS_T1 0xc0 /**< Test Mode Register Map */
130
131/* Bits in Interrupt State Register */
132#define ISR_PRX 0x01 /**< Packet Received with no errors */
133#define ISR_PTX 0x02 /**< Packet Transmitted with no errors */
134#define ISR_RXE 0x04 /**< Receive Error */
135#define ISR_TXE 0x08 /**< Transmit Error */
136#define ISR_OVW 0x10 /**< Overwrite Warning */
137#define ISR_CNT 0x20 /**< Counter Overflow */
138#define ISR_RDC 0x40 /**< Remote DMA Complete */
139#define ISR_RST 0x80 /**< Reset Status */
140
141/* Bits in Interrupt Mask Register */
142#define IMR_PRXE 0x01 /**< Packet Received Interrupt Enable */
143#define IMR_PTXE 0x02 /**< Packet Transmitted Interrupt Enable */
144#define IMR_RXEE 0x04 /**< Receive Error Interrupt Enable */
145#define IMR_TXEE 0x08 /**< Transmit Error Interrupt Enable */
146#define IMR_OVWE 0x10 /**< Overwrite Warning Interrupt Enable */
147#define IMR_CNTE 0x20 /**< Counter Overflow Interrupt Enable */
148#define IMR_RDCE 0x40 /**< DMA Complete Interrupt Enable */
149
150/* Bits in Data Configuration Register */
151#define DCR_WTS 0x01 /**< Word Transfer Select */
152#define DCR_BYTEWIDE 0x00 /**< WTS: byte wide transfers */
153#define DCR_WORDWIDE 0x01 /**< WTS: word wide transfers */
154#define DCR_BOS 0x02 /**< Byte Order Select */
155#define DCR_LTLENDIAN 0x00 /**< BOS: Little Endian */
156#define DCR_BIGENDIAN 0x02 /**< BOS: Big Endian */
157#define DCR_LAS 0x04 /**< Long Address Select */
158#define DCR_BMS 0x08 /**< Burst Mode Select */
159#define DCR_AR 0x10 /**< Autoinitialize Remote */
160#define DCR_FTS 0x60 /**< Fifo Threshold Select */
161#define DCR_2BYTES 0x00 /**< 2 bytes */
162#define DCR_4BYTES 0x40 /**< 4 bytes */
163#define DCR_8BYTES 0x20 /**< 8 bytes */
164#define DCR_12BYTES 0x60 /**< 12 bytes */
165
166/* Bits in Transmit Configuration Register */
167#define TCR_CRC 0x01 /**< Inhibit CRC */
168#define TCR_ELC 0x06 /**< Encoded Loopback Control */
169#define TCR_NORMAL 0x00 /**< ELC: Normal Operation */
170#define TCR_INTERNAL 0x02 /**< ELC: Internal Loopback */
171#define TCR_0EXTERNAL 0x04 /**< ELC: External Loopback LPBK=0 */
172#define TCR_1EXTERNAL 0x06 /**< ELC: External Loopback LPBK=1 */
173#define TCR_ATD 0x08 /**< Auto Transmit Disable */
174#define TCR_OFST 0x10 /**< Collision Offset Enable (be nice) */
175
176/* Bits in Interrupt Status Register */
177#define TSR_PTX 0x01 /**< Packet Transmitted (without error) */
178#define TSR_DFR 0x02 /**< Transmit Deferred (reserved) */
179#define TSR_COL 0x04 /**< Transmit Collided */
180#define TSR_ABT 0x08 /**< Transmit Aborted */
181#define TSR_CRS 0x10 /**< Carrier Sense Lost */
182#define TSR_FU 0x20 /**< FIFO Underrun */
183#define TSR_CDH 0x40 /**< CD Heartbeat */
184#define TSR_OWC 0x80 /**< Out of Window Collision */
185
186/* Bits in Receive Configuration Register */
187#define RCR_SEP 0x01 /**< Save Errored Packets */
188#define RCR_AR 0x02 /**< Accept Runt Packets */
189#define RCR_AB 0x04 /**< Accept Broadcast */
190#define RCR_AM 0x08 /**< Accept Multicast */
191#define RCR_PRO 0x10 /**< Physical Promiscuous */
192#define RCR_MON 0x20 /**< Monitor Mode */
193
194/* Bits in Receive Status Register */
195#define RSR_PRX 0x01 /**< Packet Received Intact */
196#define RSR_CRC 0x02 /**< CRC Error */
197#define RSR_FAE 0x04 /**< Frame Alignment Error */
198#define RSR_FO 0x08 /**< FIFO Overrun */
199#define RSR_MPA 0x10 /**< Missed Packet */
200#define RSR_PHY 0x20 /**< Multicast Address Match */
201#define RSR_DIS 0x40 /**< Receiver Disabled */
202#define RSR_DFR 0x80 /**< In later manuals: Deferring */
203
204typedef struct {
205 /* Device configuration */
206 void *port;
207 void *data_port;
208 int irq;
209 uint8_t mac[ETH_ADDR];
210
211 uint8_t start_page; /**< Ring buffer start page */
212 uint8_t stop_page; /**< Ring buffer stop page */
213
214 /* Send queue */
215 struct {
216 bool dirty; /**< Buffer contains a packet */
217 size_t size; /**< Packet size */
218 uint8_t page; /**< Starting page of the buffer */
219 } sq;
220 fibril_mutex_t sq_mutex;
221 fibril_condvar_t sq_cv;
222
223 /* Driver run-time variables */
224 bool probed;
225 bool up;
226
227 /* Device statistics */
228 device_stats_t stats;
229 uint64_t misses; /**< Receive frame misses */
230 uint64_t underruns; /**< FIFO underruns */
231 uint64_t overruns; /**< FIFO overruns */
232} ne2k_t;
233
234typedef struct {
235 link_t link;
236 packet_t *packet;
237} frame_t;
238
239extern int ne2k_probe(ne2k_t *, void *, int);
240extern int ne2k_up(ne2k_t *);
241extern void ne2k_down(ne2k_t *);
242extern void ne2k_send(ne2k_t *, packet_t *);
243extern list_t *ne2k_interrupt(ne2k_t *, uint8_t, uint8_t);
244
245#endif
246
247/** @}
248 */
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