source: mainline/uspace/srv/hw/netif/dp8390/dp8390.h@ b187536

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b187536 was b187536, checked in by Martin Decky <martin@…>, 15 years ago

more declutter
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1/** @addtogroup dp8390
2 * @{
3 */
4
5/** @file
6 * DP8390 network interface definitions.
7 */
8
9#ifndef __NET_NETIF_DP8390_H__
10#define __NET_NETIF_DP8390_H__
11
12#include <net/packet.h>
13#include "dp8390_port.h"
14
15/** Input/output size */
16#define DP8390_IO_SIZE 0x0020
17
18/* National Semiconductor DP8390 Network Interface Controller. */
19
20/** Page 0, for reading */
21#define DP_CR 0x00 /**< Command Register */
22#define DP_CLDA0 0x01 /**< Current Local DMA Address 0 */
23#define DP_CLDA1 0x02 /**< Current Local DMA Address 1 */
24#define DP_BNRY 0x03 /**< Boundary Pointer */
25#define DP_TSR 0x04 /**< Transmit Status Register */
26#define DP_NCR 0x05 /**< Number of Collisions Register */
27#define DP_FIFO 0x06 /**< FIFO */
28#define DP_ISR 0x07 /**< Interrupt Status Register */
29#define DP_CRDA0 0x08 /**< Current Remote DMA Address 0 */
30#define DP_CRDA1 0x09 /**< Current Remote DMA Address 1 */
31#define DP_RSR 0x0c /**< Receive Status Register */
32#define DP_CNTR0 0x0d /**< Tally Counter 0 */
33#define DP_CNTR1 0x0e /**< Tally Counter 1 */
34#define DP_CNTR2 0x0f /**< Tally Counter 2 */
35
36/** Page 0, for writing */
37#define DP_PSTART 0x01 /**< Page Start Register*/
38#define DP_PSTOP 0x02 /**< Page Stop Register */
39#define DP_TPSR 0x04 /**< Transmit Page Start Register */
40#define DP_TBCR0 0x05 /**< Transmit Byte Count Register 0 */
41#define DP_TBCR1 0x06 /**< Transmit Byte Count Register 1 */
42#define DP_RSAR0 0x08 /**< Remote Start Address Register 0 */
43#define DP_RSAR1 0x09 /**< Remote Start Address Register 1 */
44#define DP_RBCR0 0x0a /**< Remote Byte Count Register 0 */
45#define DP_RBCR1 0x0b /**< Remote Byte Count Register 1 */
46#define DP_RCR 0x0c /**< Receive Configuration Register */
47#define DP_TCR 0x0d /**< Transmit Configuration Register */
48#define DP_DCR 0x0e /**< Data Configuration Register */
49#define DP_IMR 0x0f /**< Interrupt Mask Register */
50
51/** Page 1, read/write */
52#define DP_PAR0 0x1 /* Physical Address Register 0 */
53#define DP_PAR1 0x2 /* Physical Address Register 1 */
54#define DP_PAR2 0x3 /* Physical Address Register 2 */
55#define DP_PAR3 0x4 /* Physical Address Register 3 */
56#define DP_PAR4 0x5 /* Physical Address Register 4 */
57#define DP_PAR5 0x6 /* Physical Address Register 5 */
58#define DP_CURR 0x7 /* Current Page Register */
59#define DP_MAR0 0x8 /* Multicast Address Register 0 */
60#define DP_MAR1 0x9 /* Multicast Address Register 1 */
61#define DP_MAR2 0xA /* Multicast Address Register 2 */
62#define DP_MAR3 0xB /* Multicast Address Register 3 */
63#define DP_MAR4 0xC /* Multicast Address Register 4 */
64#define DP_MAR5 0xD /* Multicast Address Register 5 */
65#define DP_MAR6 0xE /* Multicast Address Register 6 */
66#define DP_MAR7 0xF /* Multicast Address Register 7 */
67
68/* Bits in dp_cr */
69#define CR_STP 0x01 /* Stop: software reset */
70#define CR_STA 0x02 /* Start: activate NIC */
71#define CR_TXP 0x04 /* Transmit Packet */
72#define CR_DMA 0x38 /* Mask for DMA control */
73#define CR_DM_NOP 0x00 /* DMA: No Operation */
74#define CR_DM_RR 0x08 /* DMA: Remote Read */
75#define CR_DM_RW 0x10 /* DMA: Remote Write */
76#define CR_DM_SP 0x18 /* DMA: Send Packet */
77#define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */
78#define CR_PS 0xC0 /* Mask for Page Select */
79#define CR_PS_P0 0x00 /* Register Page 0 */
80#define CR_PS_P1 0x40 /* Register Page 1 */
81#define CR_PS_P2 0x80 /* Register Page 2 */
82#define CR_PS_T1 0xC0 /* Test Mode Register Map */
83
84/* Bits in dp_isr */
85#define ISR_PRX 0x01 /* Packet Received with no errors */
86#define ISR_PTX 0x02 /* Packet Transmitted with no errors */
87#define ISR_RXE 0x04 /* Receive Error */
88#define ISR_TXE 0x08 /* Transmit Error */
89#define ISR_OVW 0x10 /* Overwrite Warning */
90#define ISR_CNT 0x20 /* Counter Overflow */
91#define ISR_RDC 0x40 /* Remote DMA Complete */
92#define ISR_RST 0x80 /* Reset Status */
93
94/* Bits in dp_imr */
95#define IMR_PRXE 0x01 /* Packet Received iEnable */
96#define IMR_PTXE 0x02 /* Packet Transmitted iEnable */
97#define IMR_RXEE 0x04 /* Receive Error iEnable */
98#define IMR_TXEE 0x08 /* Transmit Error iEnable */
99#define IMR_OVWE 0x10 /* Overwrite Warning iEnable */
100#define IMR_CNTE 0x20 /* Counter Overflow iEnable */
101#define IMR_RDCE 0x40 /* DMA Complete iEnable */
102
103/* Bits in dp_dcr */
104#define DCR_WTS 0x01 /* Word Transfer Select */
105#define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */
106#define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */
107#define DCR_BOS 0x02 /* Byte Order Select */
108#define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */
109#define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */
110#define DCR_LAS 0x04 /* Long Address Select */
111#define DCR_BMS 0x08 /* Burst Mode Select
112 * Called Loopback Select (LS) in
113 * later manuals. Should be set. */
114#define DCR_AR 0x10 /* Autoinitialize Remote */
115#define DCR_FTS 0x60 /* Fifo Threshold Select */
116#define DCR_2BYTES 0x00 /* 2 bytes */
117#define DCR_4BYTES 0x40 /* 4 bytes */
118#define DCR_8BYTES 0x20 /* 8 bytes */
119#define DCR_12BYTES 0x60 /* 12 bytes */
120
121/* Bits in dp_tcr */
122#define TCR_CRC 0x01 /* Inhibit CRC */
123#define TCR_ELC 0x06 /* Encoded Loopback Control */
124#define TCR_NORMAL 0x00 /* ELC: Normal Operation */
125#define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */
126#define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */
127#define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */
128#define TCR_ATD 0x08 /* Auto Transmit Disable */
129#define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */
130
131/* Bits in dp_tsr */
132#define TSR_PTX 0x01 /* Packet Transmitted (without error)*/
133#define TSR_DFR 0x02 /* Transmit Deferred, reserved in
134 * later manuals. */
135#define TSR_COL 0x04 /* Transmit Collided */
136#define TSR_ABT 0x08 /* Transmit Aborted */
137#define TSR_CRS 0x10 /* Carrier Sense Lost */
138#define TSR_FU 0x20 /* FIFO Underrun */
139#define TSR_CDH 0x40 /* CD Heartbeat */
140#define TSR_OWC 0x80 /* Out of Window Collision */
141
142/* Bits in tp_rcr */
143#define RCR_SEP 0x01 /* Save Errored Packets */
144#define RCR_AR 0x02 /* Accept Runt Packets */
145#define RCR_AB 0x04 /* Accept Broadcast */
146#define RCR_AM 0x08 /* Accept Multicast */
147#define RCR_PRO 0x10 /* Physical Promiscuous */
148#define RCR_MON 0x20 /* Monitor Mode */
149
150/* Bits in dp_rsr */
151#define RSR_PRX 0x01 /* Packet Received Intact */
152#define RSR_CRC 0x02 /* CRC Error */
153#define RSR_FAE 0x04 /* Frame Alignment Error */
154#define RSR_FO 0x08 /* FIFO Overrun */
155#define RSR_MPA 0x10 /* Missed Packet */
156#define RSR_PHY 0x20 /* Multicast Address Match */
157#define RSR_DIS 0x40 /* Receiver Disabled */
158#define RSR_DFR 0x80 /* In later manuals: Deferring */
159
160/** Type definition of the receive header
161 *
162 */
163typedef struct dp_rcvhdr {
164 /** Copy of rsr */
165 uint8_t dr_status;
166
167 /** Pointer to next packet */
168 uint8_t dr_next;
169
170 /** Receive Byte Count Low */
171 uint8_t dr_rbcl;
172
173 /** Receive Byte Count High */
174 uint8_t dr_rbch;
175} dp_rcvhdr_t;
176
177/** Page size */
178#define DP_PAGESIZE 256
179
180/** Read 1 byte from the zero page register.
181 * @param[in] dep The network interface structure.
182 * @param[in] reg The register offset.
183 * @returns The read value.
184 */
185#define inb_reg0(dep, reg) (inb(dep->de_dp8390_port + reg))
186
187/** Write 1 byte zero page register.
188 * @param[in] dep The network interface structure.
189 * @param[in] reg The register offset.
190 * @param[in] data The value to be written.
191 */
192#define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port + reg, data))
193
194/** Read 1 byte from the first page register.
195 * @param[in] dep The network interface structure.
196 * @param[in] reg The register offset.
197 * @returns The read value.
198 */
199#define inb_reg1(dep, reg) (inb(dep->de_dp8390_port + reg))
200
201/** Write 1 byte first page register.
202 * @param[in] dep The network interface structure.
203 * @param[in] reg The register offset.
204 * @param[in] data The value to be written.
205 */
206#define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port + reg, data))
207
208/* Software interface to the dp8390 driver */
209
210struct dpeth;
211
212typedef void (*dp_initf_t)(struct dpeth *dep);
213typedef void (*dp_stopf_t)(struct dpeth *dep);
214typedef void (*dp_user2nicf_t)(struct dpeth *dep, void *buf, size_t offset, int nic_addr, size_t size);
215typedef void (*dp_nic2userf_t)(struct dpeth *dep, int nic_addr, void *buf, size_t offset, size_t size);
216typedef void (*dp_getblock_t)(struct dpeth *dep, int page, size_t offset, size_t size, void *dst);
217
218#define SENDQ_NR 2 /* Maximum size of the send queue */
219#define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */
220
221/** Maximum number of waiting packets to be sent or received.
222 */
223#define MAX_PACKETS 1024
224
225typedef struct dpeth {
226 /** Outgoing packets queue */
227 packet_t *packet_queue;
228
229 /** Outgoing packets count */
230 int packet_count;
231
232 /** Received packets queue */
233 packet_t *received_queue;
234
235 /** Received packets count */
236 int received_count;
237
238 /*
239 * The de_base_port field is the starting point of the probe.
240 * The conf routine also fills de_irq. If the probe
241 * routine knows the irq and/or memory address because they are
242 * hardwired in the board, the probe should modify these fields.
243 * Futhermore, the probe routine should also fill in de_initf and
244 * de_stopf fields with the appropriate function pointers.
245 */
246 port_t de_base_port;
247 int de_irq;
248 dp_initf_t de_initf;
249 dp_stopf_t de_stopf;
250 char de_name[sizeof("dp8390#n")];
251
252 /*
253 * The initf function fills the following fields. Only cards that do
254 * programmed I/O fill in the de_pata_port field.
255 * In addition, the init routine has to fill in the sendq data
256 * structures.
257 */
258 ether_addr_t de_address;
259 port_t de_dp8390_port;
260 port_t de_data_port;
261 int de_16bit;
262 long de_ramsize;
263 int de_offset_page;
264 int de_startpage;
265 int de_stoppage;
266
267 /* Do it yourself send queue */
268 struct sendq {
269 int sq_filled; /* this buffer contains a packet */
270 int sq_size; /* with this size */
271 int sq_sendpage; /* starting page of the buffer */
272 } de_sendq[SENDQ_NR];
273
274 int de_sendq_nr;
275 int de_sendq_head; /* Enqueue at the head */
276 int de_sendq_tail; /* Dequeue at the tail */
277
278 /* Fields for internal use by the dp8390 driver. */
279 int de_flags;
280 int de_mode;
281 eth_stat_t de_stat;
282 dp_user2nicf_t de_user2nicf;
283 dp_nic2userf_t de_nic2userf;
284 dp_getblock_t de_getblockf;
285} dpeth_t;
286
287#define DEF_EMPTY 0x000
288#define DEF_PACK_SEND 0x001
289#define DEF_PACK_RECV 0x002
290#define DEF_SEND_AVAIL 0x004
291#define DEF_READING 0x010
292#define DEF_PROMISC 0x040
293#define DEF_MULTI 0x080
294#define DEF_BROAD 0x100
295#define DEF_ENABLED 0x200
296#define DEF_STOPPED 0x400
297
298#define DEM_DISABLED 0x0
299#define DEM_ENABLED 0x2
300
301#endif
302
303/** @}
304 */
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