source: mainline/uspace/srv/hw/netif/dp8390/dp8390.h@ 6fc0edd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6fc0edd was 6fc0edd, checked in by Martin Decky <martin@…>, 14 years ago

more robust interrupt processing
  • Property mode set to 100644
File size: 12.4 KB
Line 
1/** @addtogroup dp8390
2 * @{
3 */
4
5/** @file
6 * DP8390 network interface definitions.
7 */
8
9#ifndef __NET_NETIF_DP8390_H__
10#define __NET_NETIF_DP8390_H__
11
12#include <net/packet.h>
13#include "dp8390_port.h"
14
15/** Input/output size */
16#define DP8390_IO_SIZE 0x0020
17
18/* National Semiconductor DP8390 Network Interface Controller. */
19
20 /* Page 0, for reading ------------- */
21#define DP_CR 0x0 /* Read side of Command Register */
22#define DP_CLDA0 0x1 /* Current Local Dma Address 0 */
23#define DP_CLDA1 0x2 /* Current Local Dma Address 1 */
24#define DP_BNRY 0x3 /* Boundary Pointer */
25#define DP_TSR 0x4 /* Transmit Status Register */
26#define DP_NCR 0x5 /* Number of Collisions Register */
27#define DP_FIFO 0x6 /* Fifo ?? */
28#define DP_ISR 0x7 /* Interrupt Status Register */
29#define DP_CRDA0 0x8 /* Current Remote Dma Address 0 */
30#define DP_CRDA1 0x9 /* Current Remote Dma Address 1 */
31#define DP_DUM1 0xA /* unused */
32#define DP_DUM2 0xB /* unused */
33#define DP_RSR 0xC /* Receive Status Register */
34#define DP_CNTR0 0xD /* Tally Counter 0 */
35#define DP_CNTR1 0xE /* Tally Counter 1 */
36#define DP_CNTR2 0xF /* Tally Counter 2 */
37
38 /* Page 0, for writing ------------- */
39#define DP_CR 0x0 /* Write side of Command Register */
40#define DP_PSTART 0x1 /* Page Start Register */
41#define DP_PSTOP 0x2 /* Page Stop Register */
42#define DP_BNRY 0x3 /* Boundary Pointer */
43#define DP_TPSR 0x4 /* Transmit Page Start Register */
44#define DP_TBCR0 0x5 /* Transmit Byte Count Register 0 */
45#define DP_TBCR1 0x6 /* Transmit Byte Count Register 1 */
46#define DP_ISR 0x7 /* Interrupt Status Register */
47#define DP_RSAR0 0x8 /* Remote Start Address Register 0 */
48#define DP_RSAR1 0x9 /* Remote Start Address Register 1 */
49#define DP_RBCR0 0xA /* Remote Byte Count Register 0 */
50#define DP_RBCR1 0xB /* Remote Byte Count Register 1 */
51#define DP_RCR 0xC /* Receive Configuration Register */
52#define DP_TCR 0xD /* Transmit Configuration Register */
53#define DP_DCR 0xE /* Data Configuration Register */
54#define DP_IMR 0xF /* Interrupt Mask Register */
55
56 /* Page 1, read/write -------------- */
57#define DP_CR 0x0 /* Command Register */
58#define DP_PAR0 0x1 /* Physical Address Register 0 */
59#define DP_PAR1 0x2 /* Physical Address Register 1 */
60#define DP_PAR2 0x3 /* Physical Address Register 2 */
61#define DP_PAR3 0x4 /* Physical Address Register 3 */
62#define DP_PAR4 0x5 /* Physical Address Register 4 */
63#define DP_PAR5 0x6 /* Physical Address Register 5 */
64#define DP_CURR 0x7 /* Current Page Register */
65#define DP_MAR0 0x8 /* Multicast Address Register 0 */
66#define DP_MAR1 0x9 /* Multicast Address Register 1 */
67#define DP_MAR2 0xA /* Multicast Address Register 2 */
68#define DP_MAR3 0xB /* Multicast Address Register 3 */
69#define DP_MAR4 0xC /* Multicast Address Register 4 */
70#define DP_MAR5 0xD /* Multicast Address Register 5 */
71#define DP_MAR6 0xE /* Multicast Address Register 6 */
72#define DP_MAR7 0xF /* Multicast Address Register 7 */
73
74/* Bits in dp_cr */
75#define CR_STP 0x01 /* Stop: software reset */
76#define CR_STA 0x02 /* Start: activate NIC */
77#define CR_TXP 0x04 /* Transmit Packet */
78#define CR_DMA 0x38 /* Mask for DMA control */
79#define CR_DM_NOP 0x00 /* DMA: No Operation */
80#define CR_DM_RR 0x08 /* DMA: Remote Read */
81#define CR_DM_RW 0x10 /* DMA: Remote Write */
82#define CR_DM_SP 0x18 /* DMA: Send Packet */
83#define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */
84#define CR_PS 0xC0 /* Mask for Page Select */
85#define CR_PS_P0 0x00 /* Register Page 0 */
86#define CR_PS_P1 0x40 /* Register Page 1 */
87#define CR_PS_P2 0x80 /* Register Page 2 */
88#define CR_PS_T1 0xC0 /* Test Mode Register Map */
89
90/* Bits in dp_isr */
91#define ISR_PRX 0x01 /* Packet Received with no errors */
92#define ISR_PTX 0x02 /* Packet Transmitted with no errors */
93#define ISR_RXE 0x04 /* Receive Error */
94#define ISR_TXE 0x08 /* Transmit Error */
95#define ISR_OVW 0x10 /* Overwrite Warning */
96#define ISR_CNT 0x20 /* Counter Overflow */
97#define ISR_RDC 0x40 /* Remote DMA Complete */
98#define ISR_RST 0x80 /* Reset Status */
99
100/* Bits in dp_imr */
101#define IMR_PRXE 0x01 /* Packet Received iEnable */
102#define IMR_PTXE 0x02 /* Packet Transmitted iEnable */
103#define IMR_RXEE 0x04 /* Receive Error iEnable */
104#define IMR_TXEE 0x08 /* Transmit Error iEnable */
105#define IMR_OVWE 0x10 /* Overwrite Warning iEnable */
106#define IMR_CNTE 0x20 /* Counter Overflow iEnable */
107#define IMR_RDCE 0x40 /* DMA Complete iEnable */
108
109/* Bits in dp_dcr */
110#define DCR_WTS 0x01 /* Word Transfer Select */
111#define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */
112#define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */
113#define DCR_BOS 0x02 /* Byte Order Select */
114#define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */
115#define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */
116#define DCR_LAS 0x04 /* Long Address Select */
117#define DCR_BMS 0x08 /* Burst Mode Select
118 * Called Loopback Select (LS) in
119 * later manuals. Should be set. */
120#define DCR_AR 0x10 /* Autoinitialize Remote */
121#define DCR_FTS 0x60 /* Fifo Threshold Select */
122#define DCR_2BYTES 0x00 /* 2 bytes */
123#define DCR_4BYTES 0x40 /* 4 bytes */
124#define DCR_8BYTES 0x20 /* 8 bytes */
125#define DCR_12BYTES 0x60 /* 12 bytes */
126
127/* Bits in dp_tcr */
128#define TCR_CRC 0x01 /* Inhibit CRC */
129#define TCR_ELC 0x06 /* Encoded Loopback Control */
130#define TCR_NORMAL 0x00 /* ELC: Normal Operation */
131#define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */
132#define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */
133#define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */
134#define TCR_ATD 0x08 /* Auto Transmit Disable */
135#define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */
136
137/* Bits in dp_tsr */
138#define TSR_PTX 0x01 /* Packet Transmitted (without error)*/
139#define TSR_DFR 0x02 /* Transmit Deferred, reserved in
140 * later manuals. */
141#define TSR_COL 0x04 /* Transmit Collided */
142#define TSR_ABT 0x08 /* Transmit Aborted */
143#define TSR_CRS 0x10 /* Carrier Sense Lost */
144#define TSR_FU 0x20 /* FIFO Underrun */
145#define TSR_CDH 0x40 /* CD Heartbeat */
146#define TSR_OWC 0x80 /* Out of Window Collision */
147
148/* Bits in tp_rcr */
149#define RCR_SEP 0x01 /* Save Errored Packets */
150#define RCR_AR 0x02 /* Accept Runt Packets */
151#define RCR_AB 0x04 /* Accept Broadcast */
152#define RCR_AM 0x08 /* Accept Multicast */
153#define RCR_PRO 0x10 /* Physical Promiscuous */
154#define RCR_MON 0x20 /* Monitor Mode */
155
156/* Bits in dp_rsr */
157#define RSR_PRX 0x01 /* Packet Received Intact */
158#define RSR_CRC 0x02 /* CRC Error */
159#define RSR_FAE 0x04 /* Frame Alignment Error */
160#define RSR_FO 0x08 /* FIFO Overrun */
161#define RSR_MPA 0x10 /* Missed Packet */
162#define RSR_PHY 0x20 /* Multicast Address Match */
163#define RSR_DIS 0x40 /* Receiver Disabled */
164#define RSR_DFR 0x80 /* In later manuals: Deferring */
165
166/** Type definition of the receive header
167 *
168 */
169typedef struct dp_rcvhdr {
170 /** Copy of rsr */
171 uint8_t dr_status;
172
173 /** Pointer to next packet */
174 uint8_t dr_next;
175
176 /** Receive Byte Count Low */
177 uint8_t dr_rbcl;
178
179 /** Receive Byte Count High */
180 uint8_t dr_rbch;
181} dp_rcvhdr_t;
182
183/** Page size */
184#define DP_PAGESIZE 256
185
186/** Reads 1 byte from the zero page register.
187 * @param[in] dep The network interface structure.
188 * @param[in] reg The register offset.
189 * @returns The read value.
190 */
191#define inb_reg0(dep, reg) (inb(dep->de_dp8390_port+reg))
192
193/** Writes 1 byte zero page register.
194 * @param[in] dep The network interface structure.
195 * @param[in] reg The register offset.
196 * @param[in] data The value to be written.
197 */
198#define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port+reg, data))
199
200/** Reads 1 byte from the first page register.
201 * @param[in] dep The network interface structure.
202 * @param[in] reg The register offset.
203 * @returns The read value.
204 */
205#define inb_reg1(dep, reg) (inb(dep->de_dp8390_port+reg))
206
207/** Writes 1 byte first page register.
208 * @param[in] dep The network interface structure.
209 * @param[in] reg The register offset.
210 * @param[in] data The value to be written.
211 */
212#define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port+reg, data))
213
214/* Software interface to the dp8390 driver */
215
216struct dpeth;
217struct iovec_dat;
218
219typedef void (*dp_initf_t)(struct dpeth *dep);
220typedef void (*dp_stopf_t)(struct dpeth *dep);
221typedef void (*dp_user2nicf_t)(struct dpeth *dep, struct iovec_dat *iovp, vir_bytes offset, int nic_addr, vir_bytes count);
222typedef void (*dp_nic2userf_t)(struct dpeth *dep, int nic_addr, struct iovec_dat *iovp, vir_bytes offset, vir_bytes count);
223typedef void (*dp_getblock_t)(struct dpeth *dep, int page, size_t offset, size_t size, void *dst);
224
225#define IOVEC_NR 1
226
227typedef struct iovec_dat {
228 iovec_t iod_iovec[IOVEC_NR];
229 int iod_iovec_s;
230 int iod_proc_nr;
231 vir_bytes iod_iovec_addr;
232} iovec_dat_t;
233
234#define SENDQ_NR 1 /* Maximum size of the send queue */
235#define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */
236
237/** Maximum number of waiting packets to be sent or received.
238 */
239#define MAX_PACKETS 4
240
241typedef struct dpeth {
242 /** Outgoing packets queue */
243 packet_t *packet_queue;
244
245 /** Outgoing packets count */
246 int packet_count;
247
248 /** Received packets queue */
249 packet_t *received_queue;
250
251 /** Received packets count */
252 int received_count;
253
254 /*
255 * The de_base_port field is the starting point of the probe.
256 * The conf routine also fills de_linmem and de_irq. If the probe
257 * routine knows the irq and/or memory address because they are
258 * hardwired in the board, the probe should modify these fields.
259 * Futhermore, the probe routine should also fill in de_initf and
260 * de_stopf fields with the appropriate function pointers.
261 */
262 port_t de_base_port;
263 phys_bytes de_linmem;
264 int de_irq;
265 dp_initf_t de_initf;
266 dp_stopf_t de_stopf;
267 char de_name[sizeof("dp8390#n")];
268
269 /*
270 * The initf function fills the following fields. Only cards that do
271 * programmed I/O fill in the de_pata_port field.
272 * In addition, the init routine has to fill in the sendq data
273 * structures.
274 */
275 ether_addr_t de_address;
276 port_t de_dp8390_port;
277 port_t de_data_port;
278 int de_16bit;
279 long de_ramsize;
280 int de_offset_page;
281 int de_startpage;
282 int de_stoppage;
283
284 /* Do it yourself send queue */
285 struct sendq {
286 int sq_filled; /* this buffer contains a packet */
287 int sq_size; /* with this size */
288 int sq_sendpage; /* starting page of the buffer */
289 } de_sendq[SENDQ_NR];
290
291 int de_sendq_nr;
292 int de_sendq_head; /* Enqueue at the head */
293 int de_sendq_tail; /* Dequeue at the tail */
294
295 /* Fields for internal use by the dp8390 driver. */
296 int de_flags;
297 int de_mode;
298 eth_stat_t de_stat;
299 iovec_dat_t de_read_iovec;
300 iovec_dat_t de_write_iovec;
301 iovec_dat_t de_tmp_iovec;
302 vir_bytes de_read_s;
303// int de_client;
304// message de_sendmsg;
305 dp_user2nicf_t de_user2nicf;
306 dp_nic2userf_t de_nic2userf;
307 dp_getblock_t de_getblockf;
308} dpeth_t;
309
310#define DEI_DEFAULT 0x8000
311
312#define DEF_EMPTY 0x000
313#define DEF_PACK_SEND 0x001
314#define DEF_PACK_RECV 0x002
315#define DEF_SEND_AVAIL 0x004
316#define DEF_READING 0x010
317#define DEF_PROMISC 0x040
318#define DEF_MULTI 0x080
319#define DEF_BROAD 0x100
320#define DEF_ENABLED 0x200
321#define DEF_STOPPED 0x400
322
323#define DEM_DISABLED 0x0
324#define DEM_SINK 0x1
325#define DEM_ENABLED 0x2
326
327#endif
328
329/** @}
330 */
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