| [e0854e3] | 1 | /*
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| 2 | * Copyright (c) 2009 Lukas Mejdrech
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| 3 | * Copyright (c) 2011 Martin Decky
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /*
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| 31 | * This code is based upon the NE2000 driver for MINIX,
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| 32 | * distributed according to a BSD-style license.
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| 33 | *
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| 34 | * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
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| 35 | * Copyright (c) 1992, 1994 Philip Homburg
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| 36 | * Copyright (c) 1996 G. Falzoni
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| 37 | *
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| 38 | */
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| 39 |
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| [21580dd] | 40 | /** @addtogroup dp8390
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| 41 | * @{
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| 42 | */
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| 43 |
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| 44 | /** @file
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| 45 | * DP8390 network interface definitions.
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| 46 | */
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| 47 |
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| 48 | #ifndef __NET_NETIF_DP8390_H__
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| 49 | #define __NET_NETIF_DP8390_H__
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| 50 |
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| [c69d327] | 51 | #include <net/packet.h>
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| [21580dd] | 52 | #include "dp8390_port.h"
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| 53 |
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| [74864ac] | 54 | /** Input/output size */
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| 55 | #define DP8390_IO_SIZE 0x0020
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| [21580dd] | 56 |
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| 57 | /* National Semiconductor DP8390 Network Interface Controller. */
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| 58 |
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| [b187536] | 59 | /** Page 0, for reading */
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| 60 | #define DP_CR 0x00 /**< Command Register */
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| 61 | #define DP_CLDA0 0x01 /**< Current Local DMA Address 0 */
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| 62 | #define DP_CLDA1 0x02 /**< Current Local DMA Address 1 */
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| 63 | #define DP_BNRY 0x03 /**< Boundary Pointer */
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| 64 | #define DP_TSR 0x04 /**< Transmit Status Register */
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| 65 | #define DP_NCR 0x05 /**< Number of Collisions Register */
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| 66 | #define DP_FIFO 0x06 /**< FIFO */
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| 67 | #define DP_ISR 0x07 /**< Interrupt Status Register */
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| 68 | #define DP_CRDA0 0x08 /**< Current Remote DMA Address 0 */
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| 69 | #define DP_CRDA1 0x09 /**< Current Remote DMA Address 1 */
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| 70 | #define DP_RSR 0x0c /**< Receive Status Register */
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| 71 | #define DP_CNTR0 0x0d /**< Tally Counter 0 */
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| 72 | #define DP_CNTR1 0x0e /**< Tally Counter 1 */
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| 73 | #define DP_CNTR2 0x0f /**< Tally Counter 2 */
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| 74 |
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| 75 | /** Page 0, for writing */
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| 76 | #define DP_PSTART 0x01 /**< Page Start Register*/
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| 77 | #define DP_PSTOP 0x02 /**< Page Stop Register */
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| 78 | #define DP_TPSR 0x04 /**< Transmit Page Start Register */
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| 79 | #define DP_TBCR0 0x05 /**< Transmit Byte Count Register 0 */
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| 80 | #define DP_TBCR1 0x06 /**< Transmit Byte Count Register 1 */
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| 81 | #define DP_RSAR0 0x08 /**< Remote Start Address Register 0 */
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| 82 | #define DP_RSAR1 0x09 /**< Remote Start Address Register 1 */
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| 83 | #define DP_RBCR0 0x0a /**< Remote Byte Count Register 0 */
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| 84 | #define DP_RBCR1 0x0b /**< Remote Byte Count Register 1 */
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| 85 | #define DP_RCR 0x0c /**< Receive Configuration Register */
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| 86 | #define DP_TCR 0x0d /**< Transmit Configuration Register */
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| 87 | #define DP_DCR 0x0e /**< Data Configuration Register */
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| 88 | #define DP_IMR 0x0f /**< Interrupt Mask Register */
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| 89 |
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| 90 | /** Page 1, read/write */
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| [66b628a] | 91 | #define DP_PAR0 0x01 /**< Physical Address Register 0 */
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| 92 | #define DP_PAR1 0x02 /**< Physical Address Register 1 */
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| 93 | #define DP_PAR2 0x03 /**< Physical Address Register 2 */
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| 94 | #define DP_PAR3 0x04 /**< Physical Address Register 3 */
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| 95 | #define DP_PAR4 0x05 /**< Physical Address Register 4 */
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| 96 | #define DP_PAR5 0x06 /**< Physical Address Register 5 */
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| 97 | #define DP_CURR 0x07 /**< Current Page Register */
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| 98 | #define DP_MAR0 0x08 /**< Multicast Address Register 0 */
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| 99 | #define DP_MAR1 0x09 /**< Multicast Address Register 1 */
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| 100 | #define DP_MAR2 0x0a /**< Multicast Address Register 2 */
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| 101 | #define DP_MAR3 0x0b /**< Multicast Address Register 3 */
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| 102 | #define DP_MAR4 0x0c /**< Multicast Address Register 4 */
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| 103 | #define DP_MAR5 0x0d /**< Multicast Address Register 5 */
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| 104 | #define DP_MAR6 0x0e /**< Multicast Address Register 6 */
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| 105 | #define DP_MAR7 0x0f /**< Multicast Address Register 7 */
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| [21580dd] | 106 |
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| 107 | /* Bits in dp_cr */
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| 108 | #define CR_STP 0x01 /* Stop: software reset */
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| 109 | #define CR_STA 0x02 /* Start: activate NIC */
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| 110 | #define CR_TXP 0x04 /* Transmit Packet */
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| 111 | #define CR_DMA 0x38 /* Mask for DMA control */
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| 112 | #define CR_DM_NOP 0x00 /* DMA: No Operation */
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| 113 | #define CR_DM_RR 0x08 /* DMA: Remote Read */
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| 114 | #define CR_DM_RW 0x10 /* DMA: Remote Write */
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| 115 | #define CR_DM_SP 0x18 /* DMA: Send Packet */
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| 116 | #define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */
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| 117 | #define CR_PS 0xC0 /* Mask for Page Select */
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| 118 | #define CR_PS_P0 0x00 /* Register Page 0 */
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| 119 | #define CR_PS_P1 0x40 /* Register Page 1 */
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| 120 | #define CR_PS_P2 0x80 /* Register Page 2 */
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| 121 | #define CR_PS_T1 0xC0 /* Test Mode Register Map */
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| 122 |
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| 123 | /* Bits in dp_isr */
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| 124 | #define ISR_PRX 0x01 /* Packet Received with no errors */
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| 125 | #define ISR_PTX 0x02 /* Packet Transmitted with no errors */
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| 126 | #define ISR_RXE 0x04 /* Receive Error */
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| 127 | #define ISR_TXE 0x08 /* Transmit Error */
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| 128 | #define ISR_OVW 0x10 /* Overwrite Warning */
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| 129 | #define ISR_CNT 0x20 /* Counter Overflow */
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| 130 | #define ISR_RDC 0x40 /* Remote DMA Complete */
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| 131 | #define ISR_RST 0x80 /* Reset Status */
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| 132 |
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| 133 | /* Bits in dp_imr */
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| 134 | #define IMR_PRXE 0x01 /* Packet Received iEnable */
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| 135 | #define IMR_PTXE 0x02 /* Packet Transmitted iEnable */
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| 136 | #define IMR_RXEE 0x04 /* Receive Error iEnable */
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| 137 | #define IMR_TXEE 0x08 /* Transmit Error iEnable */
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| 138 | #define IMR_OVWE 0x10 /* Overwrite Warning iEnable */
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| 139 | #define IMR_CNTE 0x20 /* Counter Overflow iEnable */
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| 140 | #define IMR_RDCE 0x40 /* DMA Complete iEnable */
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| 141 |
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| 142 | /* Bits in dp_dcr */
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| 143 | #define DCR_WTS 0x01 /* Word Transfer Select */
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| 144 | #define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */
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| 145 | #define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */
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| 146 | #define DCR_BOS 0x02 /* Byte Order Select */
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| 147 | #define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */
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| 148 | #define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */
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| 149 | #define DCR_LAS 0x04 /* Long Address Select */
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| 150 | #define DCR_BMS 0x08 /* Burst Mode Select
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| 151 | * Called Loopback Select (LS) in
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| 152 | * later manuals. Should be set. */
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| 153 | #define DCR_AR 0x10 /* Autoinitialize Remote */
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| 154 | #define DCR_FTS 0x60 /* Fifo Threshold Select */
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| 155 | #define DCR_2BYTES 0x00 /* 2 bytes */
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| 156 | #define DCR_4BYTES 0x40 /* 4 bytes */
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| 157 | #define DCR_8BYTES 0x20 /* 8 bytes */
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| 158 | #define DCR_12BYTES 0x60 /* 12 bytes */
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| 159 |
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| 160 | /* Bits in dp_tcr */
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| 161 | #define TCR_CRC 0x01 /* Inhibit CRC */
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| 162 | #define TCR_ELC 0x06 /* Encoded Loopback Control */
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| 163 | #define TCR_NORMAL 0x00 /* ELC: Normal Operation */
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| 164 | #define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */
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| 165 | #define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */
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| 166 | #define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */
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| 167 | #define TCR_ATD 0x08 /* Auto Transmit Disable */
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| 168 | #define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */
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| 169 |
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| 170 | /* Bits in dp_tsr */
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| 171 | #define TSR_PTX 0x01 /* Packet Transmitted (without error)*/
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| 172 | #define TSR_DFR 0x02 /* Transmit Deferred, reserved in
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| 173 | * later manuals. */
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| 174 | #define TSR_COL 0x04 /* Transmit Collided */
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| 175 | #define TSR_ABT 0x08 /* Transmit Aborted */
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| 176 | #define TSR_CRS 0x10 /* Carrier Sense Lost */
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| 177 | #define TSR_FU 0x20 /* FIFO Underrun */
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| 178 | #define TSR_CDH 0x40 /* CD Heartbeat */
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| 179 | #define TSR_OWC 0x80 /* Out of Window Collision */
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| 180 |
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| 181 | /* Bits in tp_rcr */
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| 182 | #define RCR_SEP 0x01 /* Save Errored Packets */
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| 183 | #define RCR_AR 0x02 /* Accept Runt Packets */
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| 184 | #define RCR_AB 0x04 /* Accept Broadcast */
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| 185 | #define RCR_AM 0x08 /* Accept Multicast */
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| 186 | #define RCR_PRO 0x10 /* Physical Promiscuous */
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| 187 | #define RCR_MON 0x20 /* Monitor Mode */
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| 188 |
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| 189 | /* Bits in dp_rsr */
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| 190 | #define RSR_PRX 0x01 /* Packet Received Intact */
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| 191 | #define RSR_CRC 0x02 /* CRC Error */
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| 192 | #define RSR_FAE 0x04 /* Frame Alignment Error */
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| 193 | #define RSR_FO 0x08 /* FIFO Overrun */
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| 194 | #define RSR_MPA 0x10 /* Missed Packet */
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| 195 | #define RSR_PHY 0x20 /* Multicast Address Match */
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| 196 | #define RSR_DIS 0x40 /* Receiver Disabled */
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| 197 | #define RSR_DFR 0x80 /* In later manuals: Deferring */
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| 198 |
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| [74864ac] | 199 | /** Type definition of the receive header
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| 200 | *
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| [21580dd] | 201 | */
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| [74864ac] | 202 | typedef struct dp_rcvhdr {
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| 203 | /** Copy of rsr */
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| 204 | uint8_t dr_status;
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| 205 |
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| 206 | /** Pointer to next packet */
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| 207 | uint8_t dr_next;
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| 208 |
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| 209 | /** Receive Byte Count Low */
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| 210 | uint8_t dr_rbcl;
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| 211 |
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| 212 | /** Receive Byte Count High */
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| 213 | uint8_t dr_rbch;
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| [21580dd] | 214 | } dp_rcvhdr_t;
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| 215 |
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| [74864ac] | 216 | /** Page size */
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| 217 | #define DP_PAGESIZE 256
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| [21580dd] | 218 |
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| [b187536] | 219 | /** Read 1 byte from the zero page register.
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| [21580dd] | 220 | * @param[in] dep The network interface structure.
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| 221 | * @param[in] reg The register offset.
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| 222 | * @returns The read value.
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| 223 | */
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| [40559a96] | 224 | #define inb_reg0(dep, reg) (inb(dep->de_dp8390_port + reg))
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| [21580dd] | 225 |
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| [b187536] | 226 | /** Write 1 byte zero page register.
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| [21580dd] | 227 | * @param[in] dep The network interface structure.
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| 228 | * @param[in] reg The register offset.
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| 229 | * @param[in] data The value to be written.
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| 230 | */
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| [40559a96] | 231 | #define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port + reg, data))
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| [21580dd] | 232 |
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| [b187536] | 233 | /** Read 1 byte from the first page register.
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| [21580dd] | 234 | * @param[in] dep The network interface structure.
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| 235 | * @param[in] reg The register offset.
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| 236 | * @returns The read value.
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| 237 | */
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| [40559a96] | 238 | #define inb_reg1(dep, reg) (inb(dep->de_dp8390_port + reg))
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| [21580dd] | 239 |
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| [b187536] | 240 | /** Write 1 byte first page register.
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| [21580dd] | 241 | * @param[in] dep The network interface structure.
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| 242 | * @param[in] reg The register offset.
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| 243 | * @param[in] data The value to be written.
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| 244 | */
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| [40559a96] | 245 | #define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port + reg, data))
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| [21580dd] | 246 |
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| [b187536] | 247 | #define SENDQ_NR 2 /* Maximum size of the send queue */
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| [74864ac] | 248 | #define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */
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| [21580dd] | 249 |
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| [74864ac] | 250 | typedef struct dpeth {
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| 251 | /*
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| 252 | * The de_base_port field is the starting point of the probe.
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| [d3a0af7] | 253 | * The conf routine also fills de_irq. If the probe
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| [21580dd] | 254 | * routine knows the irq and/or memory address because they are
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| 255 | * hardwired in the board, the probe should modify these fields.
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| 256 | */
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| 257 | port_t de_base_port;
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| 258 | int de_irq;
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| [d3c9b60] | 259 |
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| [21580dd] | 260 | ether_addr_t de_address;
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| 261 | port_t de_dp8390_port;
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| 262 | port_t de_data_port;
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| 263 | int de_16bit;
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| [aa8267c] | 264 | long de_ramsize;
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| [21580dd] | 265 | int de_offset_page;
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| 266 | int de_startpage;
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| 267 | int de_stoppage;
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| [d3c9b60] | 268 |
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| [21580dd] | 269 | /* Do it yourself send queue */
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| [d3c9b60] | 270 | struct sendq {
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| [74864ac] | 271 | int sq_filled; /* this buffer contains a packet */
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| 272 | int sq_size; /* with this size */
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| 273 | int sq_sendpage; /* starting page of the buffer */
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| [21580dd] | 274 | } de_sendq[SENDQ_NR];
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| [d3c9b60] | 275 |
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| [21580dd] | 276 | int de_sendq_nr;
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| [74864ac] | 277 | int de_sendq_head; /* Enqueue at the head */
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| 278 | int de_sendq_tail; /* Dequeue at the tail */
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| [d3c9b60] | 279 |
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| [21580dd] | 280 | /* Fields for internal use by the dp8390 driver. */
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| 281 | eth_stat_t de_stat;
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| [e3fe7df] | 282 |
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| 283 | /* Driver flags */
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| [66b628a] | 284 | bool up;
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| 285 | bool enabled;
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| 286 | bool stopped;
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| [e3fe7df] | 287 | bool sending;
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| 288 | bool send_avail;
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| [21580dd] | 289 | } dpeth_t;
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| 290 |
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| 291 | #endif
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| 292 |
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| 293 | /** @}
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| 294 | */
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