1 | /*
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2 | * Copyright (c) 2009 Lukas Mejdrech
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3 | * Copyright (c) 2011 Martin Decky
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4 | * All rights reserved.
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5 | *
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6 | * Redistribution and use in source and binary forms, with or without
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7 | * modification, are permitted provided that the following conditions
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8 | * are met:
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9 | *
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10 | * - Redistributions of source code must retain the above copyright
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11 | * notice, this list of conditions and the following disclaimer.
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12 | * - Redistributions in binary form must reproduce the above copyright
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13 | * notice, this list of conditions and the following disclaimer in the
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14 | * documentation and/or other materials provided with the distribution.
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15 | * - The name of the author may not be used to endorse or promote products
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16 | * derived from this software without specific prior written permission.
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17 | *
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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28 | */
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29 |
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30 | /*
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31 | * This code is based upon the NE2000 driver for MINIX,
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32 | * distributed according to a BSD-style license.
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33 | *
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34 | * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
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35 | * Copyright (c) 1992, 1994 Philip Homburg
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36 | * Copyright (c) 1996 G. Falzoni
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37 | *
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38 | */
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39 |
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40 | /** @addtogroup ne2000
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41 | * @{
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42 | */
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43 |
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44 | /** @file
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45 | *
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46 | * NE2000 (based on DP8390) network interface core implementation.
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47 | * Only the basic NE2000 PIO (ISA) interface is supported, remote
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48 | * DMA is completely absent from this code for simplicity.
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49 | *
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50 | */
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51 |
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52 | #include <assert.h>
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53 | #include <byteorder.h>
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54 | #include <errno.h>
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55 | #include <libarch/ddi.h>
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56 | #include <net/packet.h>
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57 | #include <packet_client.h>
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58 | #include "dp8390.h"
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59 |
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60 | /** Page size */
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61 | #define DP_PAGE 256
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62 |
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63 | /** 6 * DP_PAGE >= 1514 bytes */
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64 | #define SQ_PAGES 6
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65 |
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66 | /* NE2000 implementation. */
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67 |
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68 | /** NE2000 Data Register */
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69 | #define NE2K_DATA 0x0010
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70 |
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71 | /** NE2000 Reset register */
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72 | #define NE2K_RESET 0x001f
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73 |
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74 | /** NE2000 data start */
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75 | #define NE2K_START 0x4000
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76 |
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77 | /** NE2000 data size */
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78 | #define NE2K_SIZE 0x4000
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79 |
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80 | /** NE2000 retry count */
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81 | #define NE2K_RETRY 0x1000
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82 |
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83 | /** NE2000 error messages rate limiting */
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84 | #define NE2K_ERL 10
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85 |
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86 | /** Minimum Ethernet packet size in bytes */
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87 | #define ETH_MIN_PACK_SIZE 60
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88 |
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89 | /** Maximum Ethernet packet size in bytes */
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90 | #define ETH_MAX_PACK_SIZE_TAGGED 1518
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91 |
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92 | /** Type definition of the receive header
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93 | *
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94 | */
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95 | typedef struct {
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96 | /** Copy of RSR */
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97 | uint8_t status;
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98 |
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99 | /** Pointer to next packet */
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100 | uint8_t next;
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101 |
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102 | /** Receive Byte Count Low */
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103 | uint8_t rbcl;
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104 |
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105 | /** Receive Byte Count High */
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106 | uint8_t rbch;
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107 | } recv_header_t;
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108 |
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109 | /** Read a memory block word by word.
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110 | *
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111 | * @param[in] port Source address.
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112 | * @param[out] buf Destination buffer.
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113 | * @param[in] size Memory block size in bytes.
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114 | *
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115 | */
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116 | static void pio_read_buf_16(void *port, void *buf, size_t size)
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117 | {
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118 | size_t i;
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119 |
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120 | for (i = 0; (i << 1) < size; i++)
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121 | *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port));
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122 | }
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123 |
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124 | /** Write a memory block word by word.
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125 | *
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126 | * @param[in] port Destination address.
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127 | * @param[in] buf Source buffer.
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128 | * @param[in] size Memory block size in bytes.
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129 | *
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130 | */
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131 | static void pio_write_buf_16(void *port, void *buf, size_t size)
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132 | {
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133 | size_t i;
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134 |
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135 | for (i = 0; (i << 1) < size; i++)
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136 | pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i));
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137 | }
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138 |
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139 | static void ne2k_download(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
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140 | {
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141 | size_t esize = size & ~1;
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142 |
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143 | pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
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144 | pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
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145 | pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
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146 | pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
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147 | pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
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148 |
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149 | if (esize != 0) {
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150 | pio_read_buf_16(ne2k->data_port, buf, esize);
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151 | size -= esize;
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152 | buf += esize;
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153 | }
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154 |
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155 | if (size) {
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156 | assert(size == 1);
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157 |
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158 | uint16_t word = pio_read_16(ne2k->data_port);
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159 | memcpy(buf, &word, 1);
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160 | }
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161 | }
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162 |
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163 | static void ne2k_upload(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
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164 | {
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165 | size_t esize = size & ~1;
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166 |
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167 | pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
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168 | pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
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169 | pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
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170 | pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
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171 | pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
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172 |
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173 | if (esize != 0) {
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174 | pio_write_buf_16(ne2k->data_port, buf, esize);
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175 | size -= esize;
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176 | buf += esize;
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177 | }
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178 |
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179 | if (size) {
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180 | assert(size == 1);
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181 |
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182 | uint16_t word = 0;
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183 |
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184 | memcpy(&word, buf, 1);
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185 | pio_write_16(ne2k->data_port, word);
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186 | }
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187 | }
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188 |
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189 | static void ne2k_init(ne2k_t *ne2k)
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190 | {
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191 | unsigned int i;
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192 |
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193 | /* Reset the ethernet card */
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194 | uint8_t val = pio_read_8(ne2k->port + NE2K_RESET);
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195 | usleep(2000);
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196 | pio_write_8(ne2k->port + NE2K_RESET, val);
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197 | usleep(2000);
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198 |
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199 | /* Reset the DP8390 */
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200 | pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
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201 | for (i = 0; i < NE2K_RETRY; i++) {
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202 | if (pio_read_8(ne2k->port + DP_ISR) != 0)
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203 | break;
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204 | }
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205 | }
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206 |
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207 | /** Probe and initialize the network interface.
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208 | *
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209 | * @param[in,out] ne2k Network interface structure.
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210 | * @param[in] port Device address.
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211 | * @param[in] irq Device interrupt vector.
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212 | *
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213 | * @return EOK on success.
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214 | * @return EXDEV if the network interface was not recognized.
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215 | *
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216 | */
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217 | int ne2k_probe(ne2k_t *ne2k, void *port, int irq)
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218 | {
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219 | unsigned int i;
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220 |
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221 | /* General initialization */
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222 | ne2k->port = port;
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223 | ne2k->data_port = ne2k->port + NE2K_DATA;
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224 | ne2k->irq = irq;
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225 | ne2k->probed = false;
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226 | ne2k->up = false;
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227 |
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228 | ne2k_init(ne2k);
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229 |
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230 | /* Check if the DP8390 is really there */
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231 | uint8_t val = pio_read_8(ne2k->port + DP_CR);
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232 | if ((val & (CR_STP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT))
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233 | return EXDEV;
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234 |
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235 | /* Disable the receiver and init TCR and DCR */
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236 | pio_write_8(ne2k->port + DP_RCR, RCR_MON);
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237 | pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
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238 | pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
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239 |
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240 | /* Setup a transfer to get the MAC address */
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241 | pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
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242 | pio_write_8(ne2k->port + DP_RBCR1, 0);
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243 | pio_write_8(ne2k->port + DP_RSAR0, 0);
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244 | pio_write_8(ne2k->port + DP_RSAR1, 0);
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245 | pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
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246 |
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247 | for (i = 0; i < ETH_ADDR; i++)
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248 | ne2k->mac[i] = pio_read_16(ne2k->data_port);
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249 |
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250 | ne2k->probed = true;
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251 | return EOK;
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252 | }
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253 |
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254 | /** Start the network interface.
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255 | *
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256 | * @param[in,out] ne2k Network interface structure.
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257 | *
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258 | * @return EOK on success.
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259 | * @return EXDEV if the network interface is disabled.
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260 | *
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261 | */
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262 | int ne2k_up(ne2k_t *ne2k)
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263 | {
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264 | if (!ne2k->probed)
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265 | return EXDEV;
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266 |
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267 | ne2k_init(ne2k);
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268 |
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269 | /*
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270 | * Setup send queue. Use the first
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271 | * SQ_PAGES of NE2000 memory for the send
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272 | * buffer.
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273 | */
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274 | ne2k->sq.dirty = false;
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275 | ne2k->sq.page = NE2K_START / DP_PAGE;
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276 | fibril_mutex_initialize(&ne2k->sq_mutex);
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277 | fibril_condvar_initialize(&ne2k->sq_cv);
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278 |
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279 | /*
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280 | * Setup receive ring buffer. Use all the rest
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281 | * of the NE2000 memory (except the first SQ_PAGES
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282 | * reserved for the send buffer) for the receive
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283 | * ring buffer.
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284 | */
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285 | ne2k->start_page = ne2k->sq.page + SQ_PAGES;
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286 | ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE;
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287 |
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288 | /*
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289 | * Initialization of the DP8390 following the mandatory procedure
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290 | * in reference manual ("DP8390D/NS32490D NIC Network Interface
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291 | * Controller", National Semiconductor, July 1995, Page 29).
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292 | */
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293 |
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294 | /* Step 1: */
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295 | pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT);
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296 |
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297 | /* Step 2: */
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298 | pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
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299 |
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300 | /* Step 3: */
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301 | pio_write_8(ne2k->port + DP_RBCR0, 0);
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302 | pio_write_8(ne2k->port + DP_RBCR1, 0);
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303 |
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304 | /* Step 4: */
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305 | pio_write_8(ne2k->port + DP_RCR, RCR_AB);
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306 |
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307 | /* Step 5: */
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308 | pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL);
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309 |
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310 | /* Step 6: */
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311 | pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page);
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312 | pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page);
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313 | pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page);
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314 |
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315 | /* Step 7: */
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316 | pio_write_8(ne2k->port + DP_ISR, 0xff);
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317 |
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318 | /* Step 8: */
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319 | pio_write_8(ne2k->port + DP_IMR,
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320 | IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
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321 |
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322 | /* Step 9: */
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323 | pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
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324 |
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325 | pio_write_8(ne2k->port + DP_PAR0, ne2k->mac[0]);
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326 | pio_write_8(ne2k->port + DP_PAR1, ne2k->mac[1]);
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327 | pio_write_8(ne2k->port + DP_PAR2, ne2k->mac[2]);
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328 | pio_write_8(ne2k->port + DP_PAR3, ne2k->mac[3]);
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329 | pio_write_8(ne2k->port + DP_PAR4, ne2k->mac[4]);
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330 | pio_write_8(ne2k->port + DP_PAR5, ne2k->mac[5]);
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331 |
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332 | pio_write_8(ne2k->port + DP_MAR0, 0xff);
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333 | pio_write_8(ne2k->port + DP_MAR1, 0xff);
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334 | pio_write_8(ne2k->port + DP_MAR2, 0xff);
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335 | pio_write_8(ne2k->port + DP_MAR3, 0xff);
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336 | pio_write_8(ne2k->port + DP_MAR4, 0xff);
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337 | pio_write_8(ne2k->port + DP_MAR5, 0xff);
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338 | pio_write_8(ne2k->port + DP_MAR6, 0xff);
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339 | pio_write_8(ne2k->port + DP_MAR7, 0xff);
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340 |
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341 | pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1);
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342 |
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343 | /* Step 10: */
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344 | pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
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345 |
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346 | /* Step 11: */
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347 | pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
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348 |
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349 | /* Reset counters by reading */
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350 | pio_read_8(ne2k->port + DP_CNTR0);
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351 | pio_read_8(ne2k->port + DP_CNTR1);
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352 | pio_read_8(ne2k->port + DP_CNTR2);
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353 |
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354 | /* Finish the initialization */
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355 | ne2k->up = true;
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356 | return EOK;
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357 | }
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358 |
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359 | /** Stop the network interface.
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360 | *
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361 | * @param[in,out] ne2k Network interface structure.
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362 | *
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363 | */
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364 | void ne2k_down(ne2k_t *ne2k)
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365 | {
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366 | if ((ne2k->probed) && (ne2k->up)) {
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367 | pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
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368 | ne2k_init(ne2k);
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369 | ne2k->up = false;
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370 | }
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371 | }
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372 |
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373 | /** Send a frame.
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374 | *
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375 | * @param[in,out] ne2k Network interface structure.
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376 | * @param[in] packet Frame to be sent.
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377 | *
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378 | */
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379 | void ne2k_send(ne2k_t *ne2k, packet_t *packet)
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380 | {
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381 | assert(ne2k->probed);
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382 | assert(ne2k->up);
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383 |
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384 | fibril_mutex_lock(&ne2k->sq_mutex);
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385 |
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386 | while (ne2k->sq.dirty)
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387 | fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex);
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388 |
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389 | void *buf = packet_get_data(packet);
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390 | size_t size = packet_get_data_length(packet);
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391 |
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392 | if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) {
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393 | fprintf(stderr, "%s: Frame dropped (invalid size %zu bytes)\n",
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394 | NAME, size);
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395 | return;
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396 | }
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397 |
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398 | /* Upload the frame to the ethernet card */
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399 | ne2k_upload(ne2k, buf, ne2k->sq.page * DP_PAGE, size);
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400 | ne2k->sq.dirty = true;
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401 | ne2k->sq.size = size;
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402 |
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403 | /* Initialize the transfer */
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404 | pio_write_8(ne2k->port + DP_TPSR, ne2k->sq.page);
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405 | pio_write_8(ne2k->port + DP_TBCR0, size & 0xff);
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406 | pio_write_8(ne2k->port + DP_TBCR1, (size >> 8) & 0xff);
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407 | pio_write_8(ne2k->port + DP_CR, CR_TXP | CR_STA);
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408 |
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409 | fibril_mutex_unlock(&ne2k->sq_mutex);
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410 | }
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411 |
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412 | static void ne2k_reset(ne2k_t *ne2k)
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413 | {
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414 | unsigned int i;
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415 |
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416 | /* Stop the chip */
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417 | pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
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418 | pio_write_8(ne2k->port + DP_RBCR0, 0);
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419 | pio_write_8(ne2k->port + DP_RBCR1, 0);
|
---|
420 |
|
---|
421 | for (i = 0; i < NE2K_RETRY; i++) {
|
---|
422 | if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RST) != 0)
|
---|
423 | break;
|
---|
424 | }
|
---|
425 |
|
---|
426 | pio_write_8(ne2k->port + DP_TCR, TCR_1EXTERNAL | TCR_OFST);
|
---|
427 | pio_write_8(ne2k->port + DP_CR, CR_STA | CR_DM_ABORT);
|
---|
428 | pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
|
---|
429 |
|
---|
430 | /* Acknowledge the ISR_RDC (remote DMA) interrupt */
|
---|
431 | for (i = 0; i < NE2K_RETRY; i++) {
|
---|
432 | if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RDC) != 0)
|
---|
433 | break;
|
---|
434 | }
|
---|
435 |
|
---|
436 | uint8_t val = pio_read_8(ne2k->port + DP_ISR);
|
---|
437 | pio_write_8(ne2k->port + DP_ISR, val & ~ISR_RDC);
|
---|
438 |
|
---|
439 | /*
|
---|
440 | * Reset the transmit ring. If we were transmitting a frame,
|
---|
441 | * we pretend that the packet is processed. Higher layers will
|
---|
442 | * retransmit if the packet wasn't actually sent.
|
---|
443 | */
|
---|
444 | fibril_mutex_lock(&ne2k->sq_mutex);
|
---|
445 | ne2k->sq.dirty = false;
|
---|
446 | fibril_mutex_unlock(&ne2k->sq_mutex);
|
---|
447 | }
|
---|
448 |
|
---|
449 | static frame_t *ne2k_receive_frame(ne2k_t *ne2k, uint8_t page, size_t length)
|
---|
450 | {
|
---|
451 | frame_t *frame = (frame_t *) malloc(sizeof(frame_t));
|
---|
452 | if (frame == NULL)
|
---|
453 | return NULL;
|
---|
454 |
|
---|
455 | link_initialize(&frame->link);
|
---|
456 |
|
---|
457 | frame->packet = netif_packet_get_1(length);
|
---|
458 | if (frame->packet == NULL) {
|
---|
459 | free(frame);
|
---|
460 | return NULL;
|
---|
461 | }
|
---|
462 |
|
---|
463 | void *buf = packet_suffix(frame->packet, length);
|
---|
464 | bzero(buf, length);
|
---|
465 | uint8_t last = page + length / DP_PAGE;
|
---|
466 |
|
---|
467 | if (last >= ne2k->stop_page) {
|
---|
468 | size_t left = (ne2k->stop_page - page) * DP_PAGE
|
---|
469 | - sizeof(recv_header_t);
|
---|
470 |
|
---|
471 | ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
|
---|
472 | left);
|
---|
473 | ne2k_download(ne2k, buf + left, ne2k->start_page * DP_PAGE,
|
---|
474 | length - left);
|
---|
475 | } else
|
---|
476 | ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
|
---|
477 | length);
|
---|
478 |
|
---|
479 | ne2k->stats.receive_packets++;
|
---|
480 | return frame;
|
---|
481 | }
|
---|
482 |
|
---|
483 | static link_t *ne2k_receive(ne2k_t *ne2k)
|
---|
484 | {
|
---|
485 | /*
|
---|
486 | * Allocate memory for the list of received frames.
|
---|
487 | * If the allocation fails here we still receive the
|
---|
488 | * frames from the network, but they will be lost.
|
---|
489 | */
|
---|
490 | link_t *frames = (link_t *) malloc(sizeof(link_t));
|
---|
491 | if (frames != NULL)
|
---|
492 | list_initialize(frames);
|
---|
493 |
|
---|
494 | while (true) {
|
---|
495 | uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1;
|
---|
496 |
|
---|
497 | if (boundary == ne2k->stop_page)
|
---|
498 | boundary = ne2k->start_page;
|
---|
499 |
|
---|
500 | pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA);
|
---|
501 | uint8_t current = pio_read_8(ne2k->port + DP_CURR);
|
---|
502 | pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STA);
|
---|
503 |
|
---|
504 | if (current == boundary)
|
---|
505 | /* No more frames to process */
|
---|
506 | break;
|
---|
507 |
|
---|
508 | recv_header_t header;
|
---|
509 | size_t size = sizeof(header);
|
---|
510 | size_t offset = boundary * DP_PAGE;
|
---|
511 |
|
---|
512 | /* Get the frame header */
|
---|
513 | pio_write_8(ne2k->port + DP_RBCR0, size & 0xff);
|
---|
514 | pio_write_8(ne2k->port + DP_RBCR1, (size >> 8) & 0xff);
|
---|
515 | pio_write_8(ne2k->port + DP_RSAR0, offset & 0xff);
|
---|
516 | pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff);
|
---|
517 | pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
|
---|
518 |
|
---|
519 | pio_read_buf_16(ne2k->data_port, (void *) &header, size);
|
---|
520 |
|
---|
521 | size_t length =
|
---|
522 | (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size;
|
---|
523 | uint8_t next = header.next;
|
---|
524 |
|
---|
525 | if ((length < ETH_MIN_PACK_SIZE)
|
---|
526 | || (length > ETH_MAX_PACK_SIZE_TAGGED)) {
|
---|
527 | fprintf(stderr, "%s: Rant frame (%zu bytes)\n", NAME, length);
|
---|
528 | next = current;
|
---|
529 | } else if ((header.next < ne2k->start_page)
|
---|
530 | || (header.next > ne2k->stop_page)) {
|
---|
531 | fprintf(stderr, "%s: Malformed next frame %u\n", NAME,
|
---|
532 | header.next);
|
---|
533 | next = current;
|
---|
534 | } else if (header.status & RSR_FO) {
|
---|
535 | /*
|
---|
536 | * This is very serious, so we issue a warning and
|
---|
537 | * reset the buffers.
|
---|
538 | */
|
---|
539 | fprintf(stderr, "%s: FIFO overrun\n", NAME);
|
---|
540 | ne2k->overruns++;
|
---|
541 | next = current;
|
---|
542 | } else if ((header.status & RSR_PRX) && (ne2k->up)) {
|
---|
543 | if (frames != NULL) {
|
---|
544 | frame_t *frame = ne2k_receive_frame(ne2k, boundary, length);
|
---|
545 | if (frame != NULL)
|
---|
546 | list_append(&frame->link, frames);
|
---|
547 | }
|
---|
548 | }
|
---|
549 |
|
---|
550 | /*
|
---|
551 | * Update the boundary pointer
|
---|
552 | * to the value of the page
|
---|
553 | * prior to the next packet to
|
---|
554 | * be processed.
|
---|
555 | */
|
---|
556 | if (next == ne2k->start_page)
|
---|
557 | next = ne2k->stop_page - 1;
|
---|
558 | else
|
---|
559 | next--;
|
---|
560 |
|
---|
561 | pio_write_8(ne2k->port + DP_BNRY, next);
|
---|
562 | }
|
---|
563 |
|
---|
564 | return frames;
|
---|
565 | }
|
---|
566 |
|
---|
567 | link_t *ne2k_interrupt(ne2k_t *ne2k, uint8_t isr, uint8_t tsr)
|
---|
568 | {
|
---|
569 | /* List of received frames */
|
---|
570 | link_t *frames = NULL;
|
---|
571 |
|
---|
572 | if (isr & (ISR_PTX | ISR_TXE)) {
|
---|
573 | if (isr & ISR_TXE)
|
---|
574 | ne2k->stats.send_errors++;
|
---|
575 | else {
|
---|
576 | if (tsr & TSR_PTX)
|
---|
577 | ne2k->stats.send_packets++;
|
---|
578 |
|
---|
579 | if (tsr & TSR_COL)
|
---|
580 | ne2k->stats.collisions++;
|
---|
581 |
|
---|
582 | if (tsr & TSR_ABT)
|
---|
583 | ne2k->stats.send_aborted_errors++;
|
---|
584 |
|
---|
585 | if (tsr & TSR_CRS)
|
---|
586 | ne2k->stats.send_carrier_errors++;
|
---|
587 |
|
---|
588 | if (tsr & TSR_FU) {
|
---|
589 | ne2k->underruns++;
|
---|
590 | if (ne2k->underruns < NE2K_ERL)
|
---|
591 | fprintf(stderr, "%s: FIFO underrun\n", NAME);
|
---|
592 | }
|
---|
593 |
|
---|
594 | if (tsr & TSR_CDH) {
|
---|
595 | ne2k->stats.send_heartbeat_errors++;
|
---|
596 | if (ne2k->stats.send_heartbeat_errors < NE2K_ERL)
|
---|
597 | fprintf(stderr, "%s: CD heartbeat failure\n", NAME);
|
---|
598 | }
|
---|
599 |
|
---|
600 | if (tsr & TSR_OWC)
|
---|
601 | ne2k->stats.send_window_errors++;
|
---|
602 | }
|
---|
603 |
|
---|
604 | fibril_mutex_lock(&ne2k->sq_mutex);
|
---|
605 |
|
---|
606 | if (ne2k->sq.dirty) {
|
---|
607 | /* Prepare the buffer for next packet */
|
---|
608 | ne2k->sq.dirty = false;
|
---|
609 | ne2k->sq.size = 0;
|
---|
610 |
|
---|
611 | /* Signal a next frame to be sent */
|
---|
612 | fibril_condvar_broadcast(&ne2k->sq_cv);
|
---|
613 | } else {
|
---|
614 | ne2k->misses++;
|
---|
615 | if (ne2k->misses < NE2K_ERL)
|
---|
616 | fprintf(stderr, "%s: Spurious PTX interrupt\n", NAME);
|
---|
617 | }
|
---|
618 |
|
---|
619 | fibril_mutex_unlock(&ne2k->sq_mutex);
|
---|
620 | }
|
---|
621 |
|
---|
622 | if (isr & ISR_RXE)
|
---|
623 | ne2k->stats.receive_errors++;
|
---|
624 |
|
---|
625 | if (isr & ISR_CNT) {
|
---|
626 | ne2k->stats.receive_crc_errors +=
|
---|
627 | pio_read_8(ne2k->port + DP_CNTR0);
|
---|
628 | ne2k->stats.receive_frame_errors +=
|
---|
629 | pio_read_8(ne2k->port + DP_CNTR1);
|
---|
630 | ne2k->stats.receive_missed_errors +=
|
---|
631 | pio_read_8(ne2k->port + DP_CNTR2);
|
---|
632 | }
|
---|
633 |
|
---|
634 | if (isr & ISR_PRX)
|
---|
635 | frames = ne2k_receive(ne2k);
|
---|
636 |
|
---|
637 | if (isr & ISR_RST) {
|
---|
638 | /*
|
---|
639 | * The chip is stopped, and all arrived
|
---|
640 | * frames are delivered.
|
---|
641 | */
|
---|
642 | ne2k_reset(ne2k);
|
---|
643 | }
|
---|
644 |
|
---|
645 | /* Unmask interrupts to be processed in the next round */
|
---|
646 | pio_write_8(ne2k->port + DP_IMR,
|
---|
647 | IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
|
---|
648 |
|
---|
649 | return frames;
|
---|
650 | }
|
---|
651 |
|
---|
652 | /** @}
|
---|
653 | */
|
---|