source: mainline/uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c@ 8562724

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8562724 was f044e96, checked in by Martin Decky <martin@…>, 14 years ago

use systematic names

  • register_irq → irq_register
  • unregister_irq → irq_unregister
  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 * Copyright (c) 2010 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup driver_serial
30 * @{
31 */
32/**
33 * @file
34 * @brief Samsung S3C24xx on-chip UART driver.
35 *
36 * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
37 */
38
39#include <ddi.h>
40#include <libarch/ddi.h>
41#include <loc.h>
42#include <ipc/char.h>
43#include <async.h>
44#include <unistd.h>
45#include <stdio.h>
46#include <stdlib.h>
47#include <sysinfo.h>
48#include <errno.h>
49#include <inttypes.h>
50#include "s3c24xx_uart.h"
51
52#define NAME "s3c24ser"
53#define NAMESPACE "char"
54
55static irq_cmd_t uart_irq_cmds[] = {
56 {
57 .cmd = CMD_ACCEPT
58 }
59};
60
61static irq_code_t uart_irq_code = {
62 sizeof(uart_irq_cmds) / sizeof(irq_cmd_t),
63 uart_irq_cmds
64};
65
66/** S3C24xx UART instance structure */
67static s3c24xx_uart_t *uart;
68
69static void s3c24xx_uart_connection(ipc_callid_t iid, ipc_call_t *icall,
70 void *arg);
71static void s3c24xx_uart_irq_handler(ipc_callid_t iid, ipc_call_t *call);
72static int s3c24xx_uart_init(s3c24xx_uart_t *uart);
73static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte);
74
75int main(int argc, char *argv[])
76{
77 int rc;
78
79 printf(NAME ": S3C24xx on-chip UART driver\n");
80
81 rc = loc_server_register(NAME, s3c24xx_uart_connection);
82 if (rc < 0) {
83 printf(NAME ": Unable to register server.\n");
84 return -1;
85 }
86
87 uart = malloc(sizeof(s3c24xx_uart_t));
88 if (uart == NULL)
89 return -1;
90
91 if (s3c24xx_uart_init(uart) != EOK)
92 return -1;
93
94 rc = loc_service_register(NAMESPACE "/" NAME, &uart->service_id);
95 if (rc != EOK) {
96 printf(NAME ": Unable to register device %s.\n",
97 NAMESPACE "/" NAME);
98 return -1;
99 }
100
101 printf(NAME ": Registered device %s.\n", NAMESPACE "/" NAME);
102
103 printf(NAME ": Accepting connections\n");
104 task_retval(0);
105 async_manager();
106
107 /* Not reached */
108 return 0;
109}
110
111/** Character device connection handler. */
112static void s3c24xx_uart_connection(ipc_callid_t iid, ipc_call_t *icall,
113 void *arg)
114{
115 /* Answer the IPC_M_CONNECT_ME_TO call. */
116 async_answer_0(iid, EOK);
117
118 while (true) {
119 ipc_call_t call;
120 ipc_callid_t callid = async_get_call(&call);
121 sysarg_t method = IPC_GET_IMETHOD(call);
122
123 if (!method) {
124 /* The other side has hung up. */
125 async_answer_0(callid, EOK);
126 return;
127 }
128
129 async_sess_t *sess =
130 async_callback_receive_start(EXCHANGE_SERIALIZE, &call);
131 if (sess != NULL) {
132 if (uart->client_sess == NULL) {
133 uart->client_sess = sess;
134 async_answer_0(callid, EOK);
135 } else
136 async_answer_0(callid, ELIMIT);
137 } else {
138 switch (method) {
139 case CHAR_WRITE_BYTE:
140 printf(NAME ": write %" PRIun " to device\n",
141 IPC_GET_ARG1(call));
142 s3c24xx_uart_sendb(uart, (uint8_t) IPC_GET_ARG1(call));
143 async_answer_0(callid, EOK);
144 break;
145 default:
146 async_answer_0(callid, EINVAL);
147 }
148 }
149 }
150}
151
152static void s3c24xx_uart_irq_handler(ipc_callid_t iid, ipc_call_t *call)
153{
154 (void) iid; (void) call;
155
156 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
157 uint32_t data = pio_read_32(&uart->io->urxh) & 0xff;
158 uint32_t status = pio_read_32(&uart->io->uerstat);
159
160 if (uart->client_sess != NULL) {
161 async_exch_t *exch = async_exchange_begin(uart->client_sess);
162 async_msg_1(exch, CHAR_NOTIF_BYTE, data);
163 async_exchange_end(exch);
164 }
165
166 if (status != 0)
167 printf(NAME ": Error status 0x%x\n", status);
168 }
169}
170
171/** Initialize S3C24xx on-chip UART. */
172static int s3c24xx_uart_init(s3c24xx_uart_t *uart)
173{
174 void *vaddr;
175 sysarg_t inr;
176
177 if (sysinfo_get_value("s3c24xx_uart.address.physical",
178 &uart->paddr) != EOK)
179 return -1;
180
181 if (pio_enable((void *) uart->paddr, sizeof(s3c24xx_uart_io_t),
182 &vaddr) != 0)
183 return -1;
184
185 if (sysinfo_get_value("s3c24xx_uart.inr", &inr) != EOK)
186 return -1;
187
188 uart->io = vaddr;
189 uart->client_sess = NULL;
190
191 printf(NAME ": device at physical address %p, inr %" PRIun ".\n",
192 (void *) uart->paddr, inr);
193
194 async_set_interrupt_received(s3c24xx_uart_irq_handler);
195
196 irq_register(inr, device_assign_devno(), 0, &uart_irq_code);
197
198 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
199 pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
200 UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
201
202 /* Set RX interrupt to pulse mode */
203 pio_write_32(&uart->io->ucon,
204 pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
205
206 return EOK;
207}
208
209/** Send a byte to the UART. */
210static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte)
211{
212 /* Wait for space becoming available in Tx FIFO. */
213 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
214 ;
215
216 pio_write_32(&uart->io->utxh, byte);
217}
218
219/** @}
220 */
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