source: mainline/uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c@ 3d9d948

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3d9d948 was 3d9d948, checked in by Jiri Svoboda <jiri@…>, 16 years ago

Operate S3C24xx UART in FIFO mode.

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File size: 5.7 KB
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1/*
2 * Copyright (c) 2010 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup driver_serial
30 * @{
31 */
32/**
33 * @file
34 * @brief Samsung S3C24xx on-chip UART driver.
35 *
36 * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
37 */
38
39#include <ddi.h>
40#include <libarch/ddi.h>
41#include <devmap.h>
42#include <ipc/ipc.h>
43#include <ipc/char.h>
44#include <async.h>
45#include <unistd.h>
46#include <stdio.h>
47#include <stdlib.h>
48#include <sysinfo.h>
49#include <errno.h>
50
51#include "s3c24xx_uart.h"
52
53#define NAME "s3c24ser"
54#define NAMESPACE "char"
55
56/* Bits in UTRSTAT register */
57#define S3C24XX_UTRSTAT_TX_EMPTY 0x4
58#define S3C24XX_UTRSTAT_RDATA 0x1
59
60/* Bits in UFSTAT register */
61#define S3C24XX_UFSTAT_TX_FULL 0x4000
62#define S3C24XX_UFSTAT_RX_FULL 0x0040
63#define S3C24XX_UFSTAT_RX_COUNT 0x002f
64
65static irq_cmd_t uart_irq_cmds[] = {
66 {
67 .cmd = CMD_ACCEPT
68 }
69};
70
71static irq_code_t uart_irq_code = {
72 sizeof(uart_irq_cmds) / sizeof(irq_cmd_t),
73 uart_irq_cmds
74};
75
76/** S3C24xx UART instance structure */
77static s3c24xx_uart_t *uart;
78
79static void s3c24xx_uart_connection(ipc_callid_t iid, ipc_call_t *icall);
80static void s3c24xx_uart_irq_handler(ipc_callid_t iid, ipc_call_t *call);
81static int s3c24xx_uart_init(s3c24xx_uart_t *uart);
82static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte);
83
84int main(int argc, char *argv[])
85{
86 int rc;
87
88 printf(NAME ": S3C24xx on-chip UART driver\n");
89
90 rc = devmap_driver_register(NAME, s3c24xx_uart_connection);
91 if (rc < 0) {
92 printf(NAME ": Unable to register driver.\n");
93 return -1;
94 }
95
96 uart = malloc(sizeof(s3c24xx_uart_t));
97 if (uart == NULL)
98 return -1;
99
100 if (s3c24xx_uart_init(uart) != EOK)
101 return -1;
102
103 rc = devmap_device_register(NAMESPACE "/" NAME, &uart->dev_handle);
104 if (rc != EOK) {
105 devmap_hangup_phone(DEVMAP_DRIVER);
106 printf(NAME ": Unable to register device %s.\n");
107 return -1;
108 }
109
110 printf(NAME ": Registered device %s.\n", NAMESPACE "/" NAME);
111
112 printf(NAME ": Accepting connections\n");
113 task_retval(0);
114 async_manager();
115
116 /* Not reached */
117 return 0;
118}
119
120/** Character device connection handler. */
121static void s3c24xx_uart_connection(ipc_callid_t iid, ipc_call_t *icall)
122{
123 ipc_callid_t callid;
124 ipc_call_t call;
125 ipcarg_t method;
126 int retval;
127
128 /* Answer the IPC_M_CONNECT_ME_TO call. */
129 ipc_answer_0(iid, EOK);
130
131 while (1) {
132 callid = async_get_call(&call);
133 method = IPC_GET_METHOD(call);
134 switch (method) {
135 case IPC_M_PHONE_HUNGUP:
136 /* The other side has hung up. */
137 ipc_answer_0(callid, EOK);
138 return;
139 case IPC_M_CONNECT_TO_ME:
140 printf(NAME ": creating callback connection\n");
141 uart->client_phone = IPC_GET_ARG5(call);
142 retval = 0;
143 break;
144 case CHAR_WRITE_BYTE:
145 printf(NAME ": write %d to device\n",
146 IPC_GET_ARG1(call));
147 s3c24xx_uart_sendb(uart, (uint8_t) IPC_GET_ARG1(call));
148 retval = 0;
149 break;
150 default:
151 retval = EINVAL;
152 break;
153 }
154 ipc_answer_0(callid, retval);
155 }
156}
157
158static void s3c24xx_uart_irq_handler(ipc_callid_t iid, ipc_call_t *call)
159{
160 (void) iid; (void) call;
161
162 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
163 uint32_t data = pio_read_32(&uart->io->urxh) & 0xff;
164 pio_read_32(&uart->io->uerstat);
165
166 if (uart->client_phone != -1) {
167 async_msg_1(uart->client_phone, CHAR_NOTIF_BYTE,
168 data);
169 }
170 }
171}
172
173/** Initialize S3C24xx on-chip UART. */
174static int s3c24xx_uart_init(s3c24xx_uart_t *uart)
175{
176 void *vaddr;
177 sysarg_t inr;
178
179 if (sysinfo_get_value("s3c24xx_uart.address.physical",
180 &uart->paddr) != EOK)
181 return -1;
182
183 if (pio_enable((void *) uart->paddr, sizeof(s3c24xx_uart_io_t),
184 &vaddr) != 0)
185 return -1;
186
187 if (sysinfo_get_value("s3c24xx_uart.inr", &inr) != EOK)
188 return -1;
189
190 uart->io = vaddr;
191 uart->client_phone = -1;
192
193 printf(NAME ": device at physical address 0x%x, inr %d.\n",
194 uart->paddr, inr);
195
196 async_set_interrupt_received(s3c24xx_uart_irq_handler);
197
198 ipc_register_irq(inr, device_assign_devno(), 0, &uart_irq_code);
199
200 /* Disable FIFO */
201 pio_write_32(&uart->io->ufcon,
202 pio_read_32(&uart->io->ufcon) & ~0x01);
203
204 /* Set RX interrupt to pulse mode */
205 pio_write_32(&uart->io->ucon,
206 pio_read_32(&uart->io->ucon) & ~(1 << 8));
207
208 return EOK;
209}
210
211/** Send a byte to the UART. */
212static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte)
213{
214 /* Wait for space becoming available in Tx FIFO. */
215 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
216 ;
217
218 pio_write_32(&uart->io->utxh, byte);
219}
220
221/** @}
222 */
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