1 | /*
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2 | * Copyright (c) 2010 Jiri Svoboda
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** @addtogroup driver_serial
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30 | * @{
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31 | */
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32 | /**
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33 | * @file
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34 | * @brief Samsung S3C24xx on-chip UART driver.
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35 | *
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36 | * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
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37 | */
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38 |
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39 | #include <ddi.h>
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40 | #include <loc.h>
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41 | #include <ipc/char.h>
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42 | #include <async.h>
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43 | #include <stdio.h>
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44 | #include <stdlib.h>
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45 | #include <sysinfo.h>
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46 | #include <errno.h>
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47 | #include <inttypes.h>
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48 | #include "s3c24xx_uart.h"
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49 |
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50 | #define NAME "s3c24ser"
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51 | #define NAMESPACE "char"
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52 |
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53 | static irq_cmd_t uart_irq_cmds[] = {
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54 | {
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55 | .cmd = CMD_ACCEPT
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56 | }
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57 | };
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58 |
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59 | static irq_code_t uart_irq_code = {
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60 | 0,
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61 | NULL,
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62 | sizeof(uart_irq_cmds) / sizeof(irq_cmd_t),
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63 | uart_irq_cmds
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64 | };
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65 |
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66 | /** S3C24xx UART instance structure */
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67 | static s3c24xx_uart_t *uart;
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68 |
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69 | static void s3c24xx_uart_connection(ipc_callid_t, ipc_call_t *, void *);
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70 | static void s3c24xx_uart_irq_handler(ipc_callid_t, ipc_call_t *, void *);
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71 | static int s3c24xx_uart_init(s3c24xx_uart_t *);
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72 | static void s3c24xx_uart_sendb(s3c24xx_uart_t *, uint8_t);
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73 |
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74 | int main(int argc, char *argv[])
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75 | {
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76 | printf("%s: S3C24xx on-chip UART driver\n", NAME);
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77 |
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78 | async_set_fallback_port_handler(s3c24xx_uart_connection, NULL);
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79 | int rc = loc_server_register(NAME);
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80 | if (rc != EOK) {
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81 | printf("%s: Unable to register server.\n", NAME);
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82 | return rc;
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83 | }
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84 |
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85 | uart = malloc(sizeof(s3c24xx_uart_t));
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86 | if (uart == NULL)
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87 | return -1;
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88 |
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89 | if (s3c24xx_uart_init(uart) != EOK)
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90 | return -1;
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91 |
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92 | rc = loc_service_register(NAMESPACE "/" NAME, &uart->service_id);
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93 | if (rc != EOK) {
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94 | printf(NAME ": Unable to register device %s.\n",
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95 | NAMESPACE "/" NAME);
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96 | return -1;
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97 | }
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98 |
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99 | printf(NAME ": Registered device %s.\n", NAMESPACE "/" NAME);
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100 |
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101 | printf(NAME ": Accepting connections\n");
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102 | task_retval(0);
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103 | async_manager();
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104 |
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105 | /* Not reached */
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106 | return 0;
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107 | }
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108 |
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109 | /** Character device connection handler. */
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110 | static void s3c24xx_uart_connection(ipc_callid_t iid, ipc_call_t *icall,
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111 | void *arg)
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112 | {
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113 | /* Answer the IPC_M_CONNECT_ME_TO call. */
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114 | async_answer_0(iid, EOK);
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115 |
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116 | while (true) {
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117 | ipc_call_t call;
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118 | ipc_callid_t callid = async_get_call(&call);
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119 | sysarg_t method = IPC_GET_IMETHOD(call);
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120 |
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121 | if (!method) {
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122 | /* The other side has hung up. */
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123 | async_answer_0(callid, EOK);
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124 | return;
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125 | }
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126 |
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127 | async_sess_t *sess =
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128 | async_callback_receive_start(EXCHANGE_SERIALIZE, &call);
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129 | if (sess != NULL) {
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130 | if (uart->client_sess == NULL) {
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131 | uart->client_sess = sess;
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132 | async_answer_0(callid, EOK);
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133 | } else
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134 | async_answer_0(callid, ELIMIT);
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135 | } else {
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136 | switch (method) {
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137 | case CHAR_WRITE_BYTE:
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138 | printf(NAME ": write %" PRIun " to device\n",
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139 | IPC_GET_ARG1(call));
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140 | s3c24xx_uart_sendb(uart, (uint8_t) IPC_GET_ARG1(call));
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141 | async_answer_0(callid, EOK);
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142 | break;
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143 | default:
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144 | async_answer_0(callid, EINVAL);
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145 | }
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146 | }
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147 | }
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148 | }
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149 |
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150 | static void s3c24xx_uart_irq_handler(ipc_callid_t iid, ipc_call_t *call,
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151 | void *arg)
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152 | {
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153 | (void) iid;
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154 | (void) call;
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155 | (void) arg;
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156 |
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157 | while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
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158 | uint32_t data = pio_read_32(&uart->io->urxh) & 0xff;
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159 | uint32_t status = pio_read_32(&uart->io->uerstat);
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160 |
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161 | if (uart->client_sess != NULL) {
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162 | async_exch_t *exch = async_exchange_begin(uart->client_sess);
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163 | async_msg_1(exch, CHAR_NOTIF_BYTE, data);
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164 | async_exchange_end(exch);
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165 | }
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166 |
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167 | if (status != 0)
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168 | printf(NAME ": Error status 0x%x\n", status);
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169 | }
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170 | }
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171 |
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172 | /** Initialize S3C24xx on-chip UART. */
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173 | static int s3c24xx_uart_init(s3c24xx_uart_t *uart)
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174 | {
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175 | void *vaddr;
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176 | sysarg_t inr;
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177 |
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178 | if (sysinfo_get_value("s3c24xx_uart.address.physical",
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179 | &uart->paddr) != EOK)
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180 | return -1;
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181 |
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182 | if (pio_enable((void *) uart->paddr, sizeof(s3c24xx_uart_io_t),
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183 | &vaddr) != 0)
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184 | return -1;
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185 |
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186 | if (sysinfo_get_value("s3c24xx_uart.inr", &inr) != EOK)
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187 | return -1;
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188 |
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189 | uart->io = vaddr;
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190 | uart->client_sess = NULL;
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191 |
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192 | printf(NAME ": device at physical address %p, inr %" PRIun ".\n",
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193 | (void *) uart->paddr, inr);
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194 |
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195 | async_irq_subscribe(inr, s3c24xx_uart_irq_handler, NULL, &uart_irq_code);
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196 |
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197 | /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
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198 | pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
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199 | UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
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200 |
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201 | /* Set RX interrupt to pulse mode */
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202 | pio_write_32(&uart->io->ucon,
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203 | pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
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204 |
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205 | return EOK;
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206 | }
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207 |
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208 | /** Send a byte to the UART. */
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209 | static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte)
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210 | {
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211 | /* Wait for space becoming available in Tx FIFO. */
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212 | while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
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213 | ;
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214 |
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215 | pio_write_32(&uart->io->utxh, byte);
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216 | }
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217 |
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218 | /** @}
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219 | */
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