source: mainline/uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c@ 0d911ee

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0d911ee was 1b054a6f, checked in by Martin Decky <martin@…>, 14 years ago

trivial changes (error code reporting, messages)

  • Property mode set to 100644
File size: 5.9 KB
Line 
1/*
2 * Copyright (c) 2010 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup driver_serial
30 * @{
31 */
32/**
33 * @file
34 * @brief Samsung S3C24xx on-chip UART driver.
35 *
36 * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
37 */
38
39#include <ddi.h>
40#include <libarch/ddi.h>
41#include <loc.h>
42#include <ipc/char.h>
43#include <async.h>
44#include <unistd.h>
45#include <stdio.h>
46#include <stdlib.h>
47#include <sysinfo.h>
48#include <errno.h>
49#include <inttypes.h>
50#include "s3c24xx_uart.h"
51
52#define NAME "s3c24ser"
53#define NAMESPACE "char"
54
55static irq_cmd_t uart_irq_cmds[] = {
56 {
57 .cmd = CMD_ACCEPT
58 }
59};
60
61static irq_code_t uart_irq_code = {
62 0,
63 NULL,
64 sizeof(uart_irq_cmds) / sizeof(irq_cmd_t),
65 uart_irq_cmds
66};
67
68/** S3C24xx UART instance structure */
69static s3c24xx_uart_t *uart;
70
71static void s3c24xx_uart_connection(ipc_callid_t iid, ipc_call_t *icall,
72 void *arg);
73static void s3c24xx_uart_irq_handler(ipc_callid_t iid, ipc_call_t *call);
74static int s3c24xx_uart_init(s3c24xx_uart_t *uart);
75static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte);
76
77int main(int argc, char *argv[])
78{
79 printf("%s: S3C24xx on-chip UART driver\n", NAME);
80
81 async_set_client_connection(s3c24xx_uart_connection);
82 int rc = loc_server_register(NAME);
83 if (rc != EOK) {
84 printf("%s: Unable to register server.\n", NAME);
85 return rc;
86 }
87
88 uart = malloc(sizeof(s3c24xx_uart_t));
89 if (uart == NULL)
90 return -1;
91
92 if (s3c24xx_uart_init(uart) != EOK)
93 return -1;
94
95 rc = loc_service_register(NAMESPACE "/" NAME, &uart->service_id);
96 if (rc != EOK) {
97 printf(NAME ": Unable to register device %s.\n",
98 NAMESPACE "/" NAME);
99 return -1;
100 }
101
102 printf(NAME ": Registered device %s.\n", NAMESPACE "/" NAME);
103
104 printf(NAME ": Accepting connections\n");
105 task_retval(0);
106 async_manager();
107
108 /* Not reached */
109 return 0;
110}
111
112/** Character device connection handler. */
113static void s3c24xx_uart_connection(ipc_callid_t iid, ipc_call_t *icall,
114 void *arg)
115{
116 /* Answer the IPC_M_CONNECT_ME_TO call. */
117 async_answer_0(iid, EOK);
118
119 while (true) {
120 ipc_call_t call;
121 ipc_callid_t callid = async_get_call(&call);
122 sysarg_t method = IPC_GET_IMETHOD(call);
123
124 if (!method) {
125 /* The other side has hung up. */
126 async_answer_0(callid, EOK);
127 return;
128 }
129
130 async_sess_t *sess =
131 async_callback_receive_start(EXCHANGE_SERIALIZE, &call);
132 if (sess != NULL) {
133 if (uart->client_sess == NULL) {
134 uart->client_sess = sess;
135 async_answer_0(callid, EOK);
136 } else
137 async_answer_0(callid, ELIMIT);
138 } else {
139 switch (method) {
140 case CHAR_WRITE_BYTE:
141 printf(NAME ": write %" PRIun " to device\n",
142 IPC_GET_ARG1(call));
143 s3c24xx_uart_sendb(uart, (uint8_t) IPC_GET_ARG1(call));
144 async_answer_0(callid, EOK);
145 break;
146 default:
147 async_answer_0(callid, EINVAL);
148 }
149 }
150 }
151}
152
153static void s3c24xx_uart_irq_handler(ipc_callid_t iid, ipc_call_t *call)
154{
155 (void) iid; (void) call;
156
157 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
158 uint32_t data = pio_read_32(&uart->io->urxh) & 0xff;
159 uint32_t status = pio_read_32(&uart->io->uerstat);
160
161 if (uart->client_sess != NULL) {
162 async_exch_t *exch = async_exchange_begin(uart->client_sess);
163 async_msg_1(exch, CHAR_NOTIF_BYTE, data);
164 async_exchange_end(exch);
165 }
166
167 if (status != 0)
168 printf(NAME ": Error status 0x%x\n", status);
169 }
170}
171
172/** Initialize S3C24xx on-chip UART. */
173static int s3c24xx_uart_init(s3c24xx_uart_t *uart)
174{
175 void *vaddr;
176 sysarg_t inr;
177
178 if (sysinfo_get_value("s3c24xx_uart.address.physical",
179 &uart->paddr) != EOK)
180 return -1;
181
182 if (pio_enable((void *) uart->paddr, sizeof(s3c24xx_uart_io_t),
183 &vaddr) != 0)
184 return -1;
185
186 if (sysinfo_get_value("s3c24xx_uart.inr", &inr) != EOK)
187 return -1;
188
189 uart->io = vaddr;
190 uart->client_sess = NULL;
191
192 printf(NAME ": device at physical address %p, inr %" PRIun ".\n",
193 (void *) uart->paddr, inr);
194
195 async_set_interrupt_received(s3c24xx_uart_irq_handler);
196
197 irq_register(inr, device_assign_devno(), 0, &uart_irq_code);
198
199 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
200 pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
201 UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
202
203 /* Set RX interrupt to pulse mode */
204 pio_write_32(&uart->io->ucon,
205 pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
206
207 return EOK;
208}
209
210/** Send a byte to the UART. */
211static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte)
212{
213 /* Wait for space becoming available in Tx FIFO. */
214 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
215 ;
216
217 pio_write_32(&uart->io->utxh, byte);
218}
219
220/** @}
221 */
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