[a9b5b5f] | 1 | /*
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[ca48672] | 2 | * Copyright (c) 2025 Jiri Svoboda
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[a9b5b5f] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /**
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| 30 | * @file
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| 31 | * @brief Samsung S3C24xx on-chip UART driver.
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| 32 | *
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| 33 | * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
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| 34 | */
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| 35 |
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[7a6065c] | 36 | #include <async.h>
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[a9b5b5f] | 37 | #include <ddi.h>
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[7a6065c] | 38 | #include <errno.h>
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| 39 | #include <inttypes.h>
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| 40 | #include <io/chardev_srv.h>
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[15f3c3f] | 41 | #include <loc.h>
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[a9b5b5f] | 42 | #include <stdio.h>
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| 43 | #include <stdlib.h>
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| 44 | #include <sysinfo.h>
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| 45 | #include "s3c24xx_uart.h"
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| 46 |
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[5da7199] | 47 | #define NAME "s3c24ser"
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| 48 | #define NAMESPACE "char"
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[a9b5b5f] | 49 |
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| 50 | static irq_cmd_t uart_irq_cmds[] = {
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| 51 | {
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| 52 | .cmd = CMD_ACCEPT
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| 53 | }
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| 54 | };
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| 55 |
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| 56 | static irq_code_t uart_irq_code = {
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[a996ae31] | 57 | 0,
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| 58 | NULL,
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[a9b5b5f] | 59 | sizeof(uart_irq_cmds) / sizeof(irq_cmd_t),
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| 60 | uart_irq_cmds
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| 61 | };
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| 62 |
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| 63 | /** S3C24xx UART instance structure */
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| 64 | static s3c24xx_uart_t *uart;
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| 65 |
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[984a9ba] | 66 | static void s3c24xx_uart_connection(ipc_call_t *, void *);
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[01c3bb4] | 67 | static void s3c24xx_uart_irq_handler(ipc_call_t *, void *);
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[8820544] | 68 | static int s3c24xx_uart_init(s3c24xx_uart_t *);
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| 69 | static void s3c24xx_uart_sendb(s3c24xx_uart_t *, uint8_t);
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[a9b5b5f] | 70 |
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[f2d88f3] | 71 | static errno_t s3c24xx_uart_read(chardev_srv_t *, void *, size_t, size_t *,
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| 72 | chardev_flags_t);
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[b7fd2a0] | 73 | static errno_t s3c24xx_uart_write(chardev_srv_t *, const void *, size_t, size_t *);
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[7a6065c] | 74 |
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| 75 | static chardev_ops_t s3c24xx_uart_chardev_ops = {
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| 76 | .read = s3c24xx_uart_read,
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| 77 | .write = s3c24xx_uart_write
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| 78 | };
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| 79 |
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[a9b5b5f] | 80 | int main(int argc, char *argv[])
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| 81 | {
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[4c6fd56] | 82 | loc_srv_t *srv;
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| 83 |
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[1b054a6f] | 84 | printf("%s: S3C24xx on-chip UART driver\n", NAME);
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[a35b458] | 85 |
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[7a6065c] | 86 | async_set_fallback_port_handler(s3c24xx_uart_connection, uart);
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[4c6fd56] | 87 | errno_t rc = loc_server_register(NAME, &srv);
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[1b054a6f] | 88 | if (rc != EOK) {
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| 89 | printf("%s: Unable to register server.\n", NAME);
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| 90 | return rc;
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[a9b5b5f] | 91 | }
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| 92 |
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| 93 | uart = malloc(sizeof(s3c24xx_uart_t));
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[4c6fd56] | 94 | if (uart == NULL) {
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| 95 | loc_server_unregister(srv);
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[a9b5b5f] | 96 | return -1;
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[4c6fd56] | 97 | }
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[a9b5b5f] | 98 |
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[4c6fd56] | 99 | if (s3c24xx_uart_init(uart) != EOK) {
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| 100 | free(uart);
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| 101 | loc_server_unregister(srv);
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[a9b5b5f] | 102 | return -1;
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[4c6fd56] | 103 | }
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[a9b5b5f] | 104 |
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[ca48672] | 105 | rc = loc_service_register(srv, NAMESPACE "/" NAME, fallback_port_id,
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| 106 | &uart->service_id);
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[a9b5b5f] | 107 | if (rc != EOK) {
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[4c6fd56] | 108 | // XXX s3c24xx_uart_fini(uart);
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| 109 | free(uart);
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| 110 | loc_server_unregister(srv);
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[7e752b2] | 111 | printf(NAME ": Unable to register device %s.\n",
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| 112 | NAMESPACE "/" NAME);
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[a9b5b5f] | 113 | return -1;
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| 114 | }
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| 115 |
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| 116 | printf(NAME ": Registered device %s.\n", NAMESPACE "/" NAME);
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| 117 |
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| 118 | printf(NAME ": Accepting connections\n");
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| 119 | task_retval(0);
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| 120 | async_manager();
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| 121 |
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| 122 | /* Not reached */
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| 123 | return 0;
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| 124 | }
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| 125 |
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| 126 | /** Character device connection handler. */
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[984a9ba] | 127 | static void s3c24xx_uart_connection(ipc_call_t *icall, void *arg)
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[a9b5b5f] | 128 | {
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[7a6065c] | 129 | s3c24xx_uart_t *uart = (s3c24xx_uart_t *) arg;
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| 130 |
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[984a9ba] | 131 | chardev_conn(icall, &uart->cds);
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[a9b5b5f] | 132 | }
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| 133 |
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[01c3bb4] | 134 | static void s3c24xx_uart_irq_handler(ipc_call_t *call, void *arg)
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[a9b5b5f] | 135 | {
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[b7fd2a0] | 136 | errno_t rc;
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[7a6065c] | 137 |
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[8820544] | 138 | (void) call;
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| 139 | (void) arg;
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[a9b5b5f] | 140 |
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[3d9d948] | 141 | while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
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[a9b5b5f] | 142 | uint32_t data = pio_read_32(&uart->io->urxh) & 0xff;
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[1720cf9] | 143 | uint32_t status = pio_read_32(&uart->io->uerstat);
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[a9b5b5f] | 144 |
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[7a6065c] | 145 | fibril_mutex_lock(&uart->buf_lock);
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| 146 |
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| 147 | rc = circ_buf_push(&uart->cbuf, &data);
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| 148 | if (rc != EOK)
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| 149 | printf(NAME ": Buffer overrun\n");
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| 150 |
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| 151 | fibril_mutex_unlock(&uart->buf_lock);
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| 152 | fibril_condvar_broadcast(&uart->buf_cv);
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[1720cf9] | 153 |
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[07c66cf] | 154 | if (status != 0)
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[1720cf9] | 155 | printf(NAME ": Error status 0x%x\n", status);
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[a9b5b5f] | 156 | }
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| 157 | }
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| 158 |
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| 159 | /** Initialize S3C24xx on-chip UART. */
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| 160 | static int s3c24xx_uart_init(s3c24xx_uart_t *uart)
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| 161 | {
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| 162 | void *vaddr;
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| 163 | sysarg_t inr;
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| 164 |
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[7a6065c] | 165 | circ_buf_init(&uart->cbuf, uart->buf, s3c24xx_uart_buf_size, 1);
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| 166 | fibril_mutex_initialize(&uart->buf_lock);
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| 167 | fibril_condvar_initialize(&uart->buf_cv);
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| 168 |
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[a9b5b5f] | 169 | if (sysinfo_get_value("s3c24xx_uart.address.physical",
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| 170 | &uart->paddr) != EOK)
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| 171 | return -1;
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| 172 |
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| 173 | if (pio_enable((void *) uart->paddr, sizeof(s3c24xx_uart_io_t),
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| 174 | &vaddr) != 0)
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| 175 | return -1;
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| 176 |
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| 177 | if (sysinfo_get_value("s3c24xx_uart.inr", &inr) != EOK)
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| 178 | return -1;
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| 179 |
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| 180 | uart->io = vaddr;
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| 181 |
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[7e752b2] | 182 | printf(NAME ": device at physical address %p, inr %" PRIun ".\n",
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| 183 | (void *) uart->paddr, inr);
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[a9b5b5f] | 184 |
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[071a1ddb] | 185 | async_irq_subscribe(inr, s3c24xx_uart_irq_handler, NULL, &uart_irq_code, NULL);
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[a9b5b5f] | 186 |
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[1720cf9] | 187 | /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
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[07c66cf] | 188 | pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
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| 189 | UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
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[a9b5b5f] | 190 |
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| 191 | /* Set RX interrupt to pulse mode */
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| 192 | pio_write_32(&uart->io->ucon,
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[07c66cf] | 193 | pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
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[a9b5b5f] | 194 |
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[7a6065c] | 195 | chardev_srvs_init(&uart->cds);
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| 196 | uart->cds.ops = &s3c24xx_uart_chardev_ops;
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| 197 | uart->cds.sarg = uart;
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| 198 |
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[a9b5b5f] | 199 | return EOK;
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| 200 | }
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| 201 |
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| 202 | /** Send a byte to the UART. */
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| 203 | static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte)
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| 204 | {
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[3d9d948] | 205 | /* Wait for space becoming available in Tx FIFO. */
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| 206 | while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
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[a9b5b5f] | 207 | ;
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| 208 |
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| 209 | pio_write_32(&uart->io->utxh, byte);
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| 210 | }
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| 211 |
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[b7fd2a0] | 212 | static errno_t s3c24xx_uart_read(chardev_srv_t *srv, void *buf, size_t size,
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[f2d88f3] | 213 | size_t *nread, chardev_flags_t flags)
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[7a6065c] | 214 | {
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| 215 | s3c24xx_uart_t *uart = (s3c24xx_uart_t *) srv->srvs->sarg;
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| 216 | size_t p;
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| 217 | uint8_t *bp = (uint8_t *) buf;
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[b7fd2a0] | 218 | errno_t rc;
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[7a6065c] | 219 |
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| 220 | fibril_mutex_lock(&uart->buf_lock);
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| 221 |
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[f2d88f3] | 222 | while ((flags & chardev_f_nonblock) == 0 &&
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| 223 | circ_buf_nused(&uart->cbuf) == 0)
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[7a6065c] | 224 | fibril_condvar_wait(&uart->buf_cv, &uart->buf_lock);
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| 225 |
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| 226 | p = 0;
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| 227 | while (p < size) {
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| 228 | rc = circ_buf_pop(&uart->cbuf, &bp[p]);
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| 229 | if (rc != EOK)
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| 230 | break;
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| 231 | ++p;
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| 232 | }
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| 233 |
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| 234 | fibril_mutex_unlock(&uart->buf_lock);
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| 235 |
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| 236 | *nread = p;
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| 237 | return EOK;
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| 238 | }
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| 239 |
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[b7fd2a0] | 240 | static errno_t s3c24xx_uart_write(chardev_srv_t *srv, const void *data, size_t size,
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[7a6065c] | 241 | size_t *nwr)
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| 242 | {
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| 243 | s3c24xx_uart_t *uart = (s3c24xx_uart_t *) srv->srvs->sarg;
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| 244 | size_t i;
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| 245 | uint8_t *dp = (uint8_t *) data;
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| 246 |
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| 247 | for (i = 0; i < size; i++)
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[1b20da0] | 248 | s3c24xx_uart_sendb(uart, dp[i]);
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[7a6065c] | 249 |
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| 250 | *nwr = size;
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| 251 | return EOK;
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| 252 | }
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| 253 |
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[a9b5b5f] | 254 | /** @}
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| 255 | */
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