source: mainline/uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c

Last change on this file was ca48672, checked in by Jiri Svoboda <jiri@…>, 5 weeks ago

loc_service_register() needs to take a port ID argument.

  • Property mode set to 100644
File size: 6.6 KB
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[a9b5b5f]1/*
[ca48672]2 * Copyright (c) 2025 Jiri Svoboda
[a9b5b5f]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @file
31 * @brief Samsung S3C24xx on-chip UART driver.
32 *
33 * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
34 */
35
[7a6065c]36#include <async.h>
[a9b5b5f]37#include <ddi.h>
[7a6065c]38#include <errno.h>
39#include <inttypes.h>
40#include <io/chardev_srv.h>
[15f3c3f]41#include <loc.h>
[a9b5b5f]42#include <stdio.h>
43#include <stdlib.h>
44#include <sysinfo.h>
45#include "s3c24xx_uart.h"
46
[5da7199]47#define NAME "s3c24ser"
48#define NAMESPACE "char"
[a9b5b5f]49
50static irq_cmd_t uart_irq_cmds[] = {
51 {
52 .cmd = CMD_ACCEPT
53 }
54};
55
56static irq_code_t uart_irq_code = {
[a996ae31]57 0,
58 NULL,
[a9b5b5f]59 sizeof(uart_irq_cmds) / sizeof(irq_cmd_t),
60 uart_irq_cmds
61};
62
63/** S3C24xx UART instance structure */
64static s3c24xx_uart_t *uart;
65
[984a9ba]66static void s3c24xx_uart_connection(ipc_call_t *, void *);
[01c3bb4]67static void s3c24xx_uart_irq_handler(ipc_call_t *, void *);
[8820544]68static int s3c24xx_uart_init(s3c24xx_uart_t *);
69static void s3c24xx_uart_sendb(s3c24xx_uart_t *, uint8_t);
[a9b5b5f]70
[f2d88f3]71static errno_t s3c24xx_uart_read(chardev_srv_t *, void *, size_t, size_t *,
72 chardev_flags_t);
[b7fd2a0]73static errno_t s3c24xx_uart_write(chardev_srv_t *, const void *, size_t, size_t *);
[7a6065c]74
75static chardev_ops_t s3c24xx_uart_chardev_ops = {
76 .read = s3c24xx_uart_read,
77 .write = s3c24xx_uart_write
78};
79
[a9b5b5f]80int main(int argc, char *argv[])
81{
[4c6fd56]82 loc_srv_t *srv;
83
[1b054a6f]84 printf("%s: S3C24xx on-chip UART driver\n", NAME);
[a35b458]85
[7a6065c]86 async_set_fallback_port_handler(s3c24xx_uart_connection, uart);
[4c6fd56]87 errno_t rc = loc_server_register(NAME, &srv);
[1b054a6f]88 if (rc != EOK) {
89 printf("%s: Unable to register server.\n", NAME);
90 return rc;
[a9b5b5f]91 }
92
93 uart = malloc(sizeof(s3c24xx_uart_t));
[4c6fd56]94 if (uart == NULL) {
95 loc_server_unregister(srv);
[a9b5b5f]96 return -1;
[4c6fd56]97 }
[a9b5b5f]98
[4c6fd56]99 if (s3c24xx_uart_init(uart) != EOK) {
100 free(uart);
101 loc_server_unregister(srv);
[a9b5b5f]102 return -1;
[4c6fd56]103 }
[a9b5b5f]104
[ca48672]105 rc = loc_service_register(srv, NAMESPACE "/" NAME, fallback_port_id,
106 &uart->service_id);
[a9b5b5f]107 if (rc != EOK) {
[4c6fd56]108 // XXX s3c24xx_uart_fini(uart);
109 free(uart);
110 loc_server_unregister(srv);
[7e752b2]111 printf(NAME ": Unable to register device %s.\n",
112 NAMESPACE "/" NAME);
[a9b5b5f]113 return -1;
114 }
115
116 printf(NAME ": Registered device %s.\n", NAMESPACE "/" NAME);
117
118 printf(NAME ": Accepting connections\n");
119 task_retval(0);
120 async_manager();
121
122 /* Not reached */
123 return 0;
124}
125
126/** Character device connection handler. */
[984a9ba]127static void s3c24xx_uart_connection(ipc_call_t *icall, void *arg)
[a9b5b5f]128{
[7a6065c]129 s3c24xx_uart_t *uart = (s3c24xx_uart_t *) arg;
130
[984a9ba]131 chardev_conn(icall, &uart->cds);
[a9b5b5f]132}
133
[01c3bb4]134static void s3c24xx_uart_irq_handler(ipc_call_t *call, void *arg)
[a9b5b5f]135{
[b7fd2a0]136 errno_t rc;
[7a6065c]137
[8820544]138 (void) call;
139 (void) arg;
[a9b5b5f]140
[3d9d948]141 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
[a9b5b5f]142 uint32_t data = pio_read_32(&uart->io->urxh) & 0xff;
[1720cf9]143 uint32_t status = pio_read_32(&uart->io->uerstat);
[a9b5b5f]144
[7a6065c]145 fibril_mutex_lock(&uart->buf_lock);
146
147 rc = circ_buf_push(&uart->cbuf, &data);
148 if (rc != EOK)
149 printf(NAME ": Buffer overrun\n");
150
151 fibril_mutex_unlock(&uart->buf_lock);
152 fibril_condvar_broadcast(&uart->buf_cv);
[1720cf9]153
[07c66cf]154 if (status != 0)
[1720cf9]155 printf(NAME ": Error status 0x%x\n", status);
[a9b5b5f]156 }
157}
158
159/** Initialize S3C24xx on-chip UART. */
160static int s3c24xx_uart_init(s3c24xx_uart_t *uart)
161{
162 void *vaddr;
163 sysarg_t inr;
164
[7a6065c]165 circ_buf_init(&uart->cbuf, uart->buf, s3c24xx_uart_buf_size, 1);
166 fibril_mutex_initialize(&uart->buf_lock);
167 fibril_condvar_initialize(&uart->buf_cv);
168
[a9b5b5f]169 if (sysinfo_get_value("s3c24xx_uart.address.physical",
170 &uart->paddr) != EOK)
171 return -1;
172
173 if (pio_enable((void *) uart->paddr, sizeof(s3c24xx_uart_io_t),
174 &vaddr) != 0)
175 return -1;
176
177 if (sysinfo_get_value("s3c24xx_uart.inr", &inr) != EOK)
178 return -1;
179
180 uart->io = vaddr;
181
[7e752b2]182 printf(NAME ": device at physical address %p, inr %" PRIun ".\n",
183 (void *) uart->paddr, inr);
[a9b5b5f]184
[071a1ddb]185 async_irq_subscribe(inr, s3c24xx_uart_irq_handler, NULL, &uart_irq_code, NULL);
[a9b5b5f]186
[1720cf9]187 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
[07c66cf]188 pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
189 UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
[a9b5b5f]190
191 /* Set RX interrupt to pulse mode */
192 pio_write_32(&uart->io->ucon,
[07c66cf]193 pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
[a9b5b5f]194
[7a6065c]195 chardev_srvs_init(&uart->cds);
196 uart->cds.ops = &s3c24xx_uart_chardev_ops;
197 uart->cds.sarg = uart;
198
[a9b5b5f]199 return EOK;
200}
201
202/** Send a byte to the UART. */
203static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte)
204{
[3d9d948]205 /* Wait for space becoming available in Tx FIFO. */
206 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
[a9b5b5f]207 ;
208
209 pio_write_32(&uart->io->utxh, byte);
210}
211
[b7fd2a0]212static errno_t s3c24xx_uart_read(chardev_srv_t *srv, void *buf, size_t size,
[f2d88f3]213 size_t *nread, chardev_flags_t flags)
[7a6065c]214{
215 s3c24xx_uart_t *uart = (s3c24xx_uart_t *) srv->srvs->sarg;
216 size_t p;
217 uint8_t *bp = (uint8_t *) buf;
[b7fd2a0]218 errno_t rc;
[7a6065c]219
220 fibril_mutex_lock(&uart->buf_lock);
221
[f2d88f3]222 while ((flags & chardev_f_nonblock) == 0 &&
223 circ_buf_nused(&uart->cbuf) == 0)
[7a6065c]224 fibril_condvar_wait(&uart->buf_cv, &uart->buf_lock);
225
226 p = 0;
227 while (p < size) {
228 rc = circ_buf_pop(&uart->cbuf, &bp[p]);
229 if (rc != EOK)
230 break;
231 ++p;
232 }
233
234 fibril_mutex_unlock(&uart->buf_lock);
235
236 *nread = p;
237 return EOK;
238}
239
[b7fd2a0]240static errno_t s3c24xx_uart_write(chardev_srv_t *srv, const void *data, size_t size,
[7a6065c]241 size_t *nwr)
242{
243 s3c24xx_uart_t *uart = (s3c24xx_uart_t *) srv->srvs->sarg;
244 size_t i;
245 uint8_t *dp = (uint8_t *) data;
246
247 for (i = 0; i < size; i++)
[1b20da0]248 s3c24xx_uart_sendb(uart, dp[i]);
[7a6065c]249
250 *nwr = size;
251 return EOK;
252}
253
[a9b5b5f]254/** @}
255 */
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