| 1 | #ifndef PCI_REGS_H
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| 2 | #define PCI_REGS_H
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| 3 |
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| 4 | // Header types
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| 5 | #define PCI_HEADER_TYPE_DEV 0
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| 6 | #define PCI_HEADER_TYPE_BRIDGE 1
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| 7 | #define PCI_HEADER_TYPE_CARDBUS 2
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| 8 |
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| 9 | // Header type 0 and 1
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| 10 | #define PCI_VENDOR_ID 0x00
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| 11 | #define PCI_DEVICE_ID 0x02
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| 12 | #define PCI_COMMAND 0x04
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| 13 | #define PCI_STATUS 0x06
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| 14 | #define PCI_REVISION_ID 0x08
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| 15 | #define PCI_PROG_IF 0x09
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| 16 | #define PCI_SUB_CLASS 0x0A
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| 17 | #define PCI_BASE_CLASS 0x0B
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| 18 | #define PCI_CACHE_LINE_SIZE 0x0C
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| 19 | #define PCI_LATENCY_TIMER 0x0D
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| 20 | #define PCI_HEADER_TYPE 0x0E
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| 21 | #define PCI_BIST 0x0F
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| 22 |
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| 23 | #define PCI_BASE_ADDR_0 0x10
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| 24 | #define PCI_BASE_ADDR_1 0x14
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| 25 |
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| 26 | // Header type 0
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| 27 | #define PCI_BASE_ADDR_2 0x18
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| 28 | #define PCI_BASE_ADDR_3 0x1B
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| 29 | #define PCI_BASE_ADDR_4 0x20
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| 30 | #define PCI_BASE_ADDR_5 0x24
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| 31 |
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| 32 | #define PCI_CARDBUS_CIS_PTR 0x28
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| 33 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2C
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| 34 | #define PCI_SUBSYSTEM_ID 0x2E
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| 35 | #define PCI_EXP_ROM_BASE 0x30
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| 36 | #define PCI_CAP_PTR 0x34
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| 37 | #define PCI_INT_LINE 0x3C
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| 38 | #define PCI_INT_PIN 0x3D
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| 39 | #define PCI_MIN_GNT 0x3E
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| 40 | #define PCI_MAX_LAT 0x3F
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| 41 |
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| 42 | // Header type 1
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| 43 | #define PCI_BRIDGE_PRIM_BUS_NUM 0x18
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| 44 | #define PCI_BRIDGE_SEC_BUS_NUM 0x19
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| 45 | #define PCI_BRIDGE_SUBORD_BUS_NUM 0x1A
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| 46 | #define PCI_BRIDGE_SEC_LATENCY_TIMER 0x1B
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| 47 | #define PCI_BRIDGE_IO_BASE 0x1C
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| 48 | #define PCI_BRIDGE_IO_LIMIT 0x1D
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| 49 | #define PCI_BRIDGE_SEC_STATUS 0x1E
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| 50 | #define PCI_BRIDGE_MEMORY_BASE 0x20
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| 51 | #define PCI_BRIDGE_MEMORY_LIMIT 0x22
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| 52 | #define PCI_BRIDGE_PREF_MEMORY_BASE 0x24
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| 53 | #define PCI_BRIDGE_PREF_MEMORY_LIMIT 0x26
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| 54 | #define PCI_BRIDGE_PREF_MEMORY_BASE_UP 0x28
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| 55 | #define PCI_BRIDGE_PREF_MEMORY_LIMIT_UP 0x2C
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| 56 | #define PCI_BRIDGE_IO_BASE_UP 0x30
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| 57 | #define PCI_BRIDGE_IO_LIMIT_UP 0x32
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| 58 | #define PCI_BRIDGE_EXP_ROM_BASE 0x38
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| 59 | #define PCI_BRIDGE_INT_LINE 0x3C
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| 60 | #define PCI_BRIDGE_INT_PIN 0x3D
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| 61 | #define PCI_BRIDGE_CTL 0x3E
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| 62 |
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| 63 |
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| 64 |
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| 65 |
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| 66 |
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| 67 |
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| 68 | /* // from psycho spec.
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| 69 | Reserved 0x28-0x2F n/a
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| 70 | Expansion ROM 0x30 4 bytes
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| 71 | Reserved 0x34-0x3B n/a
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| 72 | Interrupt Line 0x3C 1 byte
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| 73 | Interrupt Pin 0x3D 1 byte
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| 74 | MIN_GNT 0x3E 1 byte
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| 75 | MAX_LAT 0x3F 1 byte*/
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| 76 |
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| 77 |
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| 78 | #endif
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