| 1 | /*
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| 2 | * Copyright (c) 2009 Jiri Svoboda
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup bd
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| 30 | * @{
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| 31 | */
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| 32 | /** @file ATA hardware protocol (registers, data structures).
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| 33 | */
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| 34 |
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| 35 | #ifndef __ATA_HW_H__
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| 36 | #define __ATA_HW_H__
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| 37 |
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| 38 | #include <sys/types.h>
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| 39 |
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| 40 | enum {
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| 41 | CTL_READ_START = 0,
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| 42 | CTL_WRITE_START = 1,
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| 43 | };
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| 44 |
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| 45 | enum {
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| 46 | STATUS_FAILURE = 0
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| 47 | };
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| 48 |
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| 49 | enum {
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| 50 | MAX_DISKS = 2
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| 51 | };
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| 52 |
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| 53 | /** ATA Command Register Block. */
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| 54 | typedef union {
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| 55 | /* Read/Write */
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| 56 | struct {
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| 57 | uint16_t data_port;
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| 58 | uint8_t sector_count;
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| 59 | uint8_t sector_number;
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| 60 | uint8_t cylinder_low;
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| 61 | uint8_t cylinder_high;
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| 62 | uint8_t drive_head;
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| 63 | uint8_t pad_rw0;
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| 64 | };
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| 65 |
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| 66 | /* Read Only */
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| 67 | struct {
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| 68 | uint8_t pad_ro0;
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| 69 | uint8_t error;
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| 70 | uint8_t pad_ro1[5];
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| 71 | uint8_t status;
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| 72 | };
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| 73 |
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| 74 | /* Write Only */
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| 75 | struct {
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| 76 | uint8_t pad_wo0;
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| 77 | uint8_t features;
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| 78 | uint8_t pad_wo1[5];
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| 79 | uint8_t command;
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| 80 | };
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| 81 | } ata_cmd_t;
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| 82 |
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| 83 | typedef union {
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| 84 | /* Read */
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| 85 | struct {
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| 86 | uint8_t pad0[6];
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| 87 | uint8_t alt_status;
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| 88 | uint8_t drive_address;
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| 89 | };
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| 90 |
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| 91 | /* Write */
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| 92 | struct {
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| 93 | uint8_t pad1[6];
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| 94 | uint8_t device_control;
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| 95 | uint8_t pad2;
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| 96 | };
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| 97 | } ata_ctl_t;
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| 98 |
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| 99 | enum devctl_bits {
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| 100 | DCR_SRST = 0x04, /**< Software Reset */
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| 101 | DCR_nIEN = 0x02 /**< Interrupt Enable (negated) */
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| 102 | };
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| 103 |
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| 104 | enum status_bits {
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| 105 | SR_BSY = 0x80, /**< Busy */
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| 106 | SR_DRDY = 0x40, /**< Drive Ready */
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| 107 | SR_DWF = 0x20, /**< Drive Write Fault */
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| 108 | SR_DSC = 0x10, /**< Drive Seek Complete */
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| 109 | SR_DRQ = 0x08, /**< Data Request */
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| 110 | SR_CORR = 0x04, /**< Corrected Data */
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| 111 | SR_IDX = 0x02, /**< Index */
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| 112 | SR_ERR = 0x01 /**< Error */
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| 113 | };
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| 114 |
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| 115 | enum drive_head_bits {
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| 116 | DHR_LBA = 0x40, /**< Use LBA addressing mode */
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| 117 | DHR_DRV = 0x10 /**< Select device 1 */
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| 118 | };
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| 119 |
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| 120 | enum error_bits {
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| 121 | ER_BBK = 0x80, /**< Bad Block Detected */
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| 122 | ER_UNC = 0x40, /**< Uncorrectable Data Error */
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| 123 | ER_MC = 0x20, /**< Media Changed */
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| 124 | ER_IDNF = 0x10, /**< ID Not Found */
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| 125 | ER_MCR = 0x08, /**< Media Change Request */
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| 126 | ER_ABRT = 0x04, /**< Aborted Command */
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| 127 | ER_TK0NF = 0x02, /**< Track 0 Not Found */
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| 128 | ER_AMNF = 0x01 /**< Address Mark Not Found */
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| 129 | };
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| 130 |
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| 131 | enum ata_command {
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| 132 | CMD_READ_SECTORS = 0x20,
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| 133 | CMD_READ_SECTORS_EXT = 0x24,
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| 134 | CMD_WRITE_SECTORS = 0x30,
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| 135 | CMD_WRITE_SECTORS_EXT = 0x34,
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| 136 | CMD_PACKET = 0xA0,
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| 137 | CMD_IDENTIFY_PKT_DEV = 0xA1,
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| 138 | CMD_IDENTIFY_DRIVE = 0xEC
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| 139 | };
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| 140 |
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| 141 | /** Data returned from identify device and identify packet device command. */
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| 142 | typedef struct {
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| 143 | uint16_t gen_conf;
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| 144 | uint16_t cylinders;
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| 145 | uint16_t _res2;
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| 146 | uint16_t heads;
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| 147 | uint16_t _vs4;
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| 148 | uint16_t _vs5;
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| 149 | uint16_t sectors;
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| 150 | uint16_t _vs7;
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| 151 | uint16_t _vs8;
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| 152 | uint16_t _vs9;
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| 153 |
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| 154 | uint16_t serial_number[10];
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| 155 | uint16_t _vs20;
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| 156 | uint16_t _vs21;
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| 157 | uint16_t vs_bytes;
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| 158 | uint16_t firmware_rev[4];
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| 159 | uint16_t model_name[20];
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| 160 |
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| 161 | uint16_t max_rw_multiple;
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| 162 | uint16_t _res48;
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| 163 | uint16_t caps; /* Different meaning for packet device */
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| 164 | uint16_t _res50;
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| 165 | uint16_t pio_timing;
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| 166 | uint16_t dma_timing;
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| 167 |
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| 168 | uint16_t validity;
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| 169 | uint16_t cur_cyl;
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| 170 | uint16_t cur_heads;
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| 171 | uint16_t cur_sectors;
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| 172 | uint16_t cur_capacity0;
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| 173 | uint16_t cur_capacity1;
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| 174 | uint16_t mss;
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| 175 | uint16_t total_lba28_0;
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| 176 | uint16_t total_lba28_1;
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| 177 | uint16_t sw_dma;
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| 178 | uint16_t mw_dma;
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| 179 | uint16_t pio_modes;
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| 180 | uint16_t min_mw_dma_cycle;
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| 181 | uint16_t rec_mw_dma_cycle;
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| 182 | uint16_t min_raw_pio_cycle;
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| 183 | uint16_t min_iordy_pio_cycle;
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| 184 |
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| 185 | uint16_t _res69;
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| 186 | uint16_t _res70;
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| 187 | uint16_t _res71;
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| 188 | uint16_t _res72;
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| 189 | uint16_t _res73;
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| 190 | uint16_t _res74;
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| 191 |
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| 192 | uint16_t queue_depth;
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| 193 | uint16_t _res76[1 + 79 - 76];
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| 194 | uint16_t version_maj;
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| 195 | uint16_t version_min;
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| 196 | uint16_t cmd_set0;
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| 197 | uint16_t cmd_set1;
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| 198 | uint16_t csf_sup_ext;
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| 199 | uint16_t csf_enabled0;
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| 200 | uint16_t csf_enabled1;
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| 201 | uint16_t csf_default;
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| 202 | uint16_t udma;
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| 203 |
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| 204 | uint16_t _res89[1 + 99 - 89];
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| 205 |
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| 206 | /* Total number of blocks in LBA-48 addressing */
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| 207 | uint16_t total_lba48_0;
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| 208 | uint16_t total_lba48_1;
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| 209 | uint16_t total_lba48_2;
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| 210 | uint16_t total_lba48_3;
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| 211 |
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| 212 | /* Note: more fields are defined in ATA/ATAPI-7 */
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| 213 | uint16_t _res104[1 + 127 - 104];
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| 214 | uint16_t _vs128[1 + 159 - 128];
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| 215 | uint16_t _res160[1 + 255 - 160];
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| 216 | } identify_data_t;
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| 217 |
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| 218 | /** Capability bits for register device. */
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| 219 | enum ata_regdev_caps {
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| 220 | rd_cap_iordy = 0x0800,
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| 221 | rd_cap_iordy_cbd = 0x0400,
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| 222 | rd_cap_lba = 0x0200,
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| 223 | rd_cap_dma = 0x0100
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| 224 | };
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| 225 |
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| 226 | /** Capability bits for packet device. */
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| 227 | enum ata_pktdev_caps {
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| 228 | pd_cap_ildma = 0x8000,
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| 229 | pd_cap_cmdqueue = 0x4000,
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| 230 | pd_cap_overlap = 0x2000,
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| 231 | pd_cap_need_softreset = 0x1000, /* Obsolete (ATAPI-6) */
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| 232 | pd_cap_iordy = 0x0800,
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| 233 | pd_cap_iordy_dis = 0x0400,
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| 234 | pd_cap_lba = 0x0200, /* Must be on */
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| 235 | pd_cap_dma = 0x0100
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| 236 | };
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| 237 |
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| 238 | /** Bits of @c identify_data_t.cmd_set1 */
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| 239 | enum ata_cs1 {
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| 240 | cs1_addr48 = 0x0400 /**< 48-bit address feature set */
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| 241 | };
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| 242 |
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| 243 | /** ATA packet command codes. */
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| 244 | enum ata_pkt_command {
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| 245 | PCMD_INQUIRY = 0x12,
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| 246 | PCMD_READ_12 = 0xa8
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| 247 | };
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| 248 |
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| 249 | /** ATAPI Inquiry command */
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| 250 | typedef struct {
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| 251 | uint8_t opcode; /**< Operation code (PCMD_INQUIRY) */
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| 252 | uint8_t _res0;
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| 253 | uint8_t _res1;
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| 254 | uint8_t _res2;
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| 255 | uint8_t alloc_len; /**< Allocation length */
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| 256 | uint8_t _res3;
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| 257 | uint8_t _res4;
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| 258 | uint8_t _res5;
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| 259 | uint32_t _res6;
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| 260 | } __attribute__ ((packed)) ata_pcmd_inquiry_t;
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| 261 |
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| 262 | /** ATAPI Read(12) command */
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| 263 | typedef struct {
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| 264 | uint8_t opcode; /**< Operation code (PCMD_READ_12) */
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| 265 | uint8_t _res0;
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| 266 | uint32_t ba; /**< Starting block address */
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| 267 | uint32_t nblocks; /**< Number of blocks to transfer */
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| 268 | uint8_t _res1;
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| 269 | uint8_t _res2;
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| 270 | } __attribute__ ((packed)) ata_pcmd_read_12_t;
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| 271 |
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| 272 | /** Data returned from Inquiry command (mandatory part) */
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| 273 | typedef struct {
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| 274 | uint8_t pdev_type; /** Reserved, Peripheral device type */
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| 275 | uint8_t rmb; /** RMB, Reserved */
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| 276 | uint8_t std_version; /** ISO version, ECMA version, ANSI version */
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| 277 | uint8_t atapi_ver_rdf; /** ATAPI version, Response data format */
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| 278 | uint8_t additional_len; /** Additional length */
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| 279 | uint8_t _res0;
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| 280 | uint8_t _res1;
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| 281 | uint8_t _res2;
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| 282 | uint8_t vendor_id[8]; /** Vendor ID */
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| 283 | uint8_t product_id[8]; /** Product ID */
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| 284 | uint8_t product_rev[4]; /** Product revision level */
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| 285 | } ata_inquiry_data_t;
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| 286 |
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| 287 | /** Extract value of ata_inquiry_data_t.pdev_type */
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| 288 | #define INQUIRY_PDEV_TYPE(val) ((val) & 0x1f)
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| 289 |
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| 290 | /** Values for ata_inquiry_data_t.pdev_type */
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| 291 | enum ata_pdev_type {
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| 292 | PDEV_TYPE_CDROM = 0x05
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| 293 | };
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| 294 |
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| 295 | #endif
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| 296 |
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| 297 | /** @}
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| 298 | */
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