[2d4faf7] | 1 | /*
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| 2 | * Copyright (c) 2018 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @file VIRTIO support
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| 30 | */
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| 31 |
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| 32 | #include "virtio-pci.h"
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| 33 |
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| 34 | #include <as.h>
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| 35 | #include <align.h>
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| 36 | #include <macros.h>
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| 37 |
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| 38 | #include <ddf/log.h>
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[c1ba24a] | 39 | #include <libarch/barrier.h>
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| 40 |
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[3d135e9] | 41 | void virtio_virtq_desc_set(virtio_dev_t *vdev, uint16_t num, uint16_t descno,
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[c1ba24a] | 42 | uint64_t addr, uint32_t len, uint16_t flags, uint16_t next)
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| 43 | {
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| 44 | virtq_desc_t *d = &vdev->queues[num].desc[descno];
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[9af56b6] | 45 | pio_write_le64(&d->addr, addr);
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| 46 | pio_write_le32(&d->len, len);
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| 47 | pio_write_le16(&d->flags, flags);
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| 48 | pio_write_le16(&d->next, next);
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[c1ba24a] | 49 | }
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| 50 |
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[3d135e9] | 51 | uint16_t virtio_virtq_desc_get_next(virtio_dev_t *vdev, uint16_t num,
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| 52 | uint16_t descno)
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| 53 | {
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| 54 | virtq_desc_t *d = &vdev->queues[num].desc[descno];
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| 55 | if (!(pio_read_le16(&d->flags) & VIRTQ_DESC_F_NEXT))
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| 56 | return (uint16_t) -1U;
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| 57 | return pio_read_le16(&d->next);
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| 58 | }
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| 59 |
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[c1ba24a] | 60 | void virtio_virtq_produce_available(virtio_dev_t *vdev, uint16_t num,
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| 61 | uint16_t descno)
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| 62 | {
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| 63 | virtq_t *q = &vdev->queues[num];
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| 64 |
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[417aaafb] | 65 | fibril_mutex_lock(&q->lock);
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[9af56b6] | 66 | uint16_t idx = pio_read_le16(&q->avail->idx);
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[9afd2a8] | 67 | pio_write_le16(&q->avail->ring[idx % q->queue_size], descno);
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[c1ba24a] | 68 | write_barrier();
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[9afd2a8] | 69 | pio_write_le16(&q->avail->idx, idx + 1);
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[c1ba24a] | 70 | write_barrier();
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[9af56b6] | 71 | pio_write_le16(q->notify, num);
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[417aaafb] | 72 | fibril_mutex_unlock(&q->lock);
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[c1ba24a] | 73 | }
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[2d4faf7] | 74 |
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[b8ef198b] | 75 | bool virtio_virtq_consume_used(virtio_dev_t *vdev, uint16_t num,
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| 76 | uint16_t *descno, uint32_t *len)
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| 77 | {
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| 78 | virtq_t *q = &vdev->queues[num];
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| 79 |
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[417aaafb] | 80 | fibril_mutex_lock(&q->lock);
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[b8ef198b] | 81 | uint16_t last_idx = q->used_last_idx % q->queue_size;
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[417aaafb] | 82 | if (last_idx == (pio_read_le16(&q->used->idx) % q->queue_size)) {
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| 83 | fibril_mutex_unlock(&q->lock);
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[b8ef198b] | 84 | return false;
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[417aaafb] | 85 | }
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[b8ef198b] | 86 |
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| 87 | *descno = (uint16_t) pio_read_le32(&q->used->ring[last_idx].id);
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| 88 | *len = pio_read_le32(&q->used->ring[last_idx].len);
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| 89 |
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| 90 | q->used_last_idx++;
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[417aaafb] | 91 | fibril_mutex_unlock(&q->lock);
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[b8ef198b] | 92 |
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| 93 | return true;
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| 94 | }
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| 95 |
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[0180c67] | 96 | errno_t virtio_virtq_setup(virtio_dev_t *vdev, uint16_t num, uint16_t size)
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[2d4faf7] | 97 | {
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| 98 | virtq_t *q = &vdev->queues[num];
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| 99 | virtio_pci_common_cfg_t *cfg = vdev->common_cfg;
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| 100 |
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| 101 | /* Program the queue of our interest */
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[9af56b6] | 102 | pio_write_le16(&cfg->queue_select, num);
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[2d4faf7] | 103 |
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| 104 | /* Trim the size of the queue as needed */
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[ee0c03a] | 105 | if (size > pio_read_16(&cfg->queue_size)) {
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| 106 | ddf_msg(LVL_ERROR, "Virtq %u: not enough descriptors", num);
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| 107 | return ENOMEM;
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| 108 | }
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[9af56b6] | 109 | pio_write_le16(&cfg->queue_size, size);
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[ee0c03a] | 110 | ddf_msg(LVL_NOTE, "Virtq %u: %u descriptors", num, (unsigned) size);
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[2d4faf7] | 111 |
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| 112 | size_t avail_offset = 0;
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| 113 | size_t used_offset = 0;
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| 114 |
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| 115 | /*
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| 116 | * Compute the size of the needed DMA memory and also the offsets of
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| 117 | * the individual components
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| 118 | */
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| 119 | size_t mem_size = sizeof(virtq_desc_t[size]);
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| 120 | mem_size = ALIGN_UP(mem_size, _Alignof(virtq_avail_t));
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| 121 | avail_offset = mem_size;
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| 122 | mem_size += sizeof(virtq_avail_t) + sizeof(ioport16_t[size]) +
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| 123 | sizeof(ioport16_t);
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| 124 | mem_size = ALIGN_UP(mem_size, _Alignof(virtq_used_t));
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| 125 | used_offset = mem_size;
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| 126 | mem_size += sizeof(virtq_used_t) + sizeof(virtq_used_elem_t[size]) +
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| 127 | sizeof(ioport16_t);
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| 128 |
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| 129 | /*
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[0180c67] | 130 | * Allocate DMA memory for the virtqueues
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[2d4faf7] | 131 | */
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| 132 | q->virt = AS_AREA_ANY;
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[5b5c286] | 133 | errno_t rc = dmamem_map_anonymous(mem_size, 0,
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[2d4faf7] | 134 | AS_AREA_READ | AS_AREA_WRITE, 0, &q->phys, &q->virt);
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| 135 | if (rc != EOK) {
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| 136 | q->virt = NULL;
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| 137 | return rc;
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| 138 | }
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| 139 |
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[417aaafb] | 140 | fibril_mutex_initialize(&q->lock);
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| 141 |
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[2d4faf7] | 142 | q->size = mem_size;
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| 143 | q->queue_size = size;
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| 144 | q->desc = q->virt;
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| 145 | q->avail = q->virt + avail_offset;
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| 146 | q->used = q->virt + used_offset;
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[b8ef198b] | 147 | q->used_last_idx = 0;
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[2d4faf7] | 148 |
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| 149 | memset(q->virt, 0, q->size);
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| 150 |
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| 151 | /*
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| 152 | * Write the configured addresses to device's common config
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| 153 | */
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[9af56b6] | 154 | pio_write_le64(&cfg->queue_desc, q->phys);
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| 155 | pio_write_le64(&cfg->queue_avail, q->phys + avail_offset);
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| 156 | pio_write_le64(&cfg->queue_used, q->phys + used_offset);
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[2d4faf7] | 157 |
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| 158 | ddf_msg(LVL_NOTE, "DMA memory for virtq %d: virt=%p, phys=%p, size=%zu",
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| 159 | num, q->virt, (void *) q->phys, q->size);
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| 160 |
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[eda41a9e] | 161 | /* Determine virtq's notification address */
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| 162 | q->notify = vdev->notify_base +
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[9af56b6] | 163 | pio_read_le16(&cfg->queue_notif_off) * vdev->notify_off_multiplier;
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[eda41a9e] | 164 |
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| 165 | ddf_msg(LVL_NOTE, "notification register: %p", q->notify);
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| 166 |
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[cede6f8] | 167 | /* Enable the queue */
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| 168 | pio_write_le16(&cfg->queue_enable, 1);
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| 169 | ddf_msg(LVL_NOTE, "virtq %d set", num);
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| 170 |
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[2d4faf7] | 171 | return rc;
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| 172 | }
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| 173 |
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| 174 | void virtio_virtq_teardown(virtio_dev_t *vdev, uint16_t num)
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| 175 | {
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[cede6f8] | 176 | virtio_pci_common_cfg_t *cfg = vdev->common_cfg;
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| 177 |
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| 178 | /* Disable the queue */
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| 179 | pio_write_le16(&cfg->queue_enable, 0);
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| 180 |
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[2d4faf7] | 181 | virtq_t *q = &vdev->queues[num];
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| 182 | if (q->size)
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| 183 | dmamem_unmap_anonymous(q->virt);
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| 184 | }
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| 185 |
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| 186 | /**
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| 187 | * Perform device initialization as described in section 3.1.1 of the
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| 188 | * specification, steps 1 - 6.
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| 189 | */
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| 190 | errno_t virtio_device_setup_start(virtio_dev_t *vdev, uint32_t features)
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| 191 | {
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| 192 | virtio_pci_common_cfg_t *cfg = vdev->common_cfg;
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| 193 |
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| 194 | /* 1. Reset the device */
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| 195 | uint8_t status = VIRTIO_DEV_STATUS_RESET;
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| 196 | pio_write_8(&cfg->device_status, status);
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| 197 |
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| 198 | /* 2. Acknowledge we found the device */
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| 199 | status |= VIRTIO_DEV_STATUS_ACKNOWLEDGE;
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| 200 | pio_write_8(&cfg->device_status, status);
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| 201 |
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| 202 | /* 3. We know how to drive the device */
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| 203 | status |= VIRTIO_DEV_STATUS_DRIVER;
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| 204 | pio_write_8(&cfg->device_status, status);
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| 205 |
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| 206 | /* 4. Read the offered feature flags */
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[9af56b6] | 207 | pio_write_le32(&cfg->device_feature_select, VIRTIO_FEATURES_0_31);
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| 208 | uint32_t device_features = pio_read_le32(&cfg->device_feature);
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[2d4faf7] | 209 |
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| 210 | ddf_msg(LVL_NOTE, "offered features %x", device_features);
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| 211 |
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[3f1d4d5] | 212 | if (features != (features & device_features))
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[2d4faf7] | 213 | return ENOTSUP;
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[3f1d4d5] | 214 | features &= device_features;
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[2d4faf7] | 215 |
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| 216 | /* 4. Write the accepted feature flags */
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[9af56b6] | 217 | pio_write_le32(&cfg->driver_feature_select, VIRTIO_FEATURES_0_31);
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| 218 | pio_write_le32(&cfg->driver_feature, features);
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[2d4faf7] | 219 |
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| 220 | ddf_msg(LVL_NOTE, "accepted features %x", features);
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| 221 |
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| 222 | /* 5. Set FEATURES_OK */
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| 223 | status |= VIRTIO_DEV_STATUS_FEATURES_OK;
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| 224 | pio_write_8(&cfg->device_status, status);
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| 225 |
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[eda41a9e] | 226 | /* 6. Test if the device supports our feature subset */
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[2d4faf7] | 227 | status = pio_read_8(&cfg->device_status);
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| 228 | if (!(status & VIRTIO_DEV_STATUS_FEATURES_OK))
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| 229 | return ENOTSUP;
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| 230 |
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| 231 | return EOK;
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| 232 | }
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| 233 |
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| 234 | /**
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| 235 | * Perform device initialization as described in section 3.1.1 of the
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| 236 | * specification, step 8 (go live).
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| 237 | */
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| 238 | void virtio_device_setup_finalize(virtio_dev_t *vdev)
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| 239 | {
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| 240 | virtio_pci_common_cfg_t *cfg = vdev->common_cfg;
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| 241 |
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| 242 | /* 8. Go live */
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| 243 | uint8_t status = pio_read_8(&cfg->device_status);
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| 244 | pio_write_8(&cfg->device_status, status | VIRTIO_DEV_STATUS_DRIVER_OK);
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| 245 | }
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| 246 |
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| 247 | void virtio_device_setup_fail(virtio_dev_t *vdev)
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| 248 | {
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| 249 | virtio_pci_common_cfg_t *cfg = vdev->common_cfg;
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| 250 |
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| 251 | uint8_t status = pio_read_8(&cfg->device_status);
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| 252 | pio_write_8(&cfg->device_status, status | VIRTIO_DEV_STATUS_FAILED);
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| 253 | }
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| 254 |
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| 255 | /** @}
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| 256 | */
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