source: mainline/uspace/lib/virtio/virtio-pci.c@ 9e9ced0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9e9ced0 was 9e9ced0, checked in by Jakub Jermar <jakub@…>, 8 years ago

Return also the size of the enabled resource
  • Property mode set to 100644
File size: 5.6 KB
Line 
1/*
2 * Copyright (c) 2018 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file VIRTIO support
30 */
31
32#include "virtio-pci.h"
33
34#include <ddf/driver.h>
35#include <ddf/log.h>
36#include <pci_dev_iface.h>
37
38static bool check_bar(virtio_dev_t *vdev, uint8_t bar)
39{
40 /* We must ignore the capability if bar is greater than 5 */
41 if (bar >= PCI_BAR_COUNT)
42 return false;
43
44 /* This is not a mapped BAR */
45 if (!vdev->bar[bar].mapped)
46 return false;
47
48 return true;
49}
50
51static void virtio_pci_common_cfg(virtio_dev_t *vdev, uint8_t bar,
52 uint32_t offset, uint32_t length)
53{
54 if (vdev->common_cfg)
55 return;
56
57 if (!check_bar(vdev, bar))
58 return;
59
60 vdev->common_cfg = vdev->bar[bar].mapped_base + offset;
61
62 ddf_msg(LVL_NOTE, "common_cfg=%p", vdev->common_cfg);
63}
64
65static void virtio_pci_notify_cfg(virtio_dev_t *vdev, uint8_t bar,
66 uint32_t offset, uint32_t length, uint32_t multiplier)
67{
68 if (vdev->notify_base)
69 return;
70
71 if (!check_bar(vdev, bar))
72 return;
73
74 vdev->notify_base = vdev->bar[bar].mapped_base + offset;
75 vdev->notify_off_multiplier = multiplier;
76
77 ddf_msg(LVL_NOTE, "notify_base=%p, off_multiplier=%u",
78 vdev->notify_base, vdev->notify_off_multiplier);
79}
80
81static void virtio_pci_isr_cfg(virtio_dev_t *vdev, uint8_t bar, uint32_t offset,
82 uint32_t length)
83{
84 if (vdev->isr)
85 return;
86
87 if (!check_bar(vdev, bar))
88 return;
89
90 vdev->isr = vdev->bar[bar].mapped_base + offset;
91
92 ddf_msg(LVL_NOTE, "isr=%p", vdev->isr);
93}
94
95static void virtio_pci_device_cfg(virtio_dev_t *vdev, uint8_t bar,
96 uint32_t offset, uint32_t length)
97{
98 if (vdev->device_cfg)
99 return;
100
101 if (!check_bar(vdev, bar))
102 return;
103
104 vdev->device_cfg = vdev->bar[bar].mapped_base + offset;
105
106 ddf_msg(LVL_NOTE, "device_cfg=%p", vdev->device_cfg);
107}
108
109errno_t virtio_pci_dev_init(ddf_dev_t *dev, virtio_dev_t *vdev)
110{
111 memset(vdev, 0, sizeof(virtio_dev_t));
112
113 async_sess_t *pci_sess = ddf_dev_parent_sess_get(dev);
114 if (!pci_sess)
115 return ENOENT;
116
117 pio_window_t pio_window;
118 errno_t rc = pio_window_get(pci_sess, &pio_window);
119 if (rc != EOK)
120 return rc;
121
122 hw_resource_list_t hw_res;
123 rc = hw_res_get_resource_list(pci_sess, &hw_res);
124 if (rc != EOK)
125 return rc;
126
127 /*
128 * Enable resources and reconstruct the mapping between BAR and resource
129 * indices. We are going to need this later when the VIRTIO PCI
130 * capabilities refer to specific BARs.
131 *
132 * XXX: The mapping should probably be provided by the PCI driver
133 * itself.
134 */
135 for (unsigned i = 0, j = 0; i < PCI_BAR_COUNT && j < hw_res.count;
136 i++) {
137 /* Detect and skip unused BARs */
138 uint32_t bar;
139 rc = pci_config_space_read_32(pci_sess,
140 PCI_BAR0 + i * sizeof(uint32_t), &bar);
141 if (!bar)
142 continue;
143
144 rc = pio_enable_resource(&pio_window, &hw_res.resources[j],
145 &vdev->bar[i].mapped_base, NULL);
146 if (rc == EOK)
147 vdev->bar[i].mapped = true;
148 j++;
149 }
150
151 /*
152 * Find the VIRTIO PCI Capabilities
153 */
154 uint8_t c;
155 uint8_t id;
156 for (rc = pci_config_space_cap_first(pci_sess, &c, &id);
157 (rc == EOK) && c;
158 rc = pci_config_space_cap_next(pci_sess, &c, &id)) {
159 if (id == PCI_CAP_VENDORSPECID) {
160 uint8_t type;
161 rc = pci_config_space_read_8(pci_sess,
162 VIRTIO_PCI_CAP_TYPE(c), &type);
163 if (rc != EOK)
164 return rc;
165
166 uint8_t bar;
167 rc = pci_config_space_read_8(pci_sess,
168 VIRTIO_PCI_CAP_BAR(c), &bar);
169 if (rc != EOK)
170 return rc;
171
172 uint32_t offset;
173 rc = pci_config_space_read_32(pci_sess,
174 VIRTIO_PCI_CAP_OFFSET(c), &offset);
175 if (rc != EOK)
176 return rc;
177
178 uint32_t length;
179 rc = pci_config_space_read_32(pci_sess,
180 VIRTIO_PCI_CAP_LENGTH(c), &length);
181 if (rc != EOK)
182 return rc;
183
184 uint32_t multiplier;
185 switch (type) {
186 case VIRTIO_PCI_CAP_COMMON_CFG:
187 virtio_pci_common_cfg(vdev, bar, offset,
188 length);
189 break;
190 case VIRTIO_PCI_CAP_NOTIFY_CFG:
191 rc = pci_config_space_read_32(pci_sess,
192 VIRTIO_PCI_CAP_END(c), &multiplier);
193 if (rc != EOK)
194 return rc;
195 virtio_pci_notify_cfg(vdev, bar, offset, length,
196 multiplier);
197 break;
198 case VIRTIO_PCI_CAP_ISR_CFG:
199 virtio_pci_isr_cfg(vdev, bar, offset, length);
200 break;
201 case VIRTIO_PCI_CAP_DEVICE_CFG:
202 virtio_pci_device_cfg(vdev, bar, offset,
203 length);
204 break;
205 case VIRTIO_PCI_CAP_PCI_CFG:
206 break;
207 default:
208 break;
209 }
210 }
211 }
212
213 return rc;
214}
215
216/** @}
217 */
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