[6ce42e85] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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[e0a5d4c] | 3 | * Copyright (c) 2018 Ondrej Hlavaty
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[6ce42e85] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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[f527f58] | 29 |
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[17412546] | 30 | /** @addtogroup libusbhost
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[6ce42e85] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | * @brief UHCI host controller driver structure
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| 35 | */
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| 36 |
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[6a32665d] | 37 | #include <assert.h>
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[f527f58] | 38 | #include <atomic.h>
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[41924f30] | 39 | #include <mem.h>
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| 40 | #include <stdlib.h>
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[32fb6bce] | 41 | #include <str_error.h>
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| 42 | #include <usb/debug.h>
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[9efad54] | 43 | #include <usb/descriptor.h>
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[32fb6bce] | 44 | #include <usb/host/hcd.h>
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[944f8fdd] | 45 | #include <usb/host/utility.h>
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[6ce42e85] | 46 |
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[64fea02] | 47 | #include "usb_transfer_batch.h"
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| 48 | #include "bus.h"
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| 49 |
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| 50 | #include "endpoint.h"
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| 51 |
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[1102eca] | 52 | /**
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| 53 | * Initialize provided endpoint structure.
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[17412546] | 54 | */
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[9efad54] | 55 | void endpoint_init(endpoint_t *ep, device_t *dev, const usb_endpoint_descriptors_t *desc)
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[6ce42e85] | 56 | {
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[41924f30] | 57 | memset(ep, 0, sizeof(endpoint_t));
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[a76b01b4] | 58 |
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[6832245] | 59 | assert(dev);
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| 60 | ep->device = dev;
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| 61 |
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[41924f30] | 62 | atomic_set(&ep->refcnt, 0);
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| 63 | fibril_condvar_initialize(&ep->avail);
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[6832245] | 64 |
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[9efad54] | 65 | ep->endpoint = USB_ED_GET_EP(desc->endpoint);
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| 66 | ep->direction = USB_ED_GET_DIR(desc->endpoint);
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| 67 | ep->transfer_type = USB_ED_GET_TRANSFER_TYPE(desc->endpoint);
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| 68 | ep->max_packet_size = USB_ED_GET_MPS(desc->endpoint);
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| 69 | ep->packets_per_uframe = USB_ED_GET_ADD_OPPS(desc->endpoint) + 1;
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[6832245] | 70 |
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[9efad54] | 71 | /** Direction both is our construct never present in descriptors */
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| 72 | if (ep->transfer_type == USB_TRANSFER_CONTROL)
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| 73 | ep->direction = USB_DIRECTION_BOTH;
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| 74 |
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| 75 | ep->max_transfer_size = ep->max_packet_size * ep->packets_per_uframe;
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[c21e6a5] | 76 | ep->transfer_buffer_policy = DMA_POLICY_STRICT;
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[1d758fc] | 77 | ep->required_transfer_buffer_policy = DMA_POLICY_STRICT;
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[6832245] | 78 | }
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| 79 |
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[1102eca] | 80 | /**
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| 81 | * Get the bus endpoint belongs to.
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| 82 | */
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[6832245] | 83 | static inline const bus_ops_t *get_bus_ops(endpoint_t *ep)
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| 84 | {
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| 85 | return ep->device->bus->ops;
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[6ce42e85] | 86 | }
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[a76b01b4] | 87 |
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[1102eca] | 88 | /**
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| 89 | * Increase the reference count on endpoint.
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| 90 | */
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[41924f30] | 91 | void endpoint_add_ref(endpoint_t *ep)
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[f527f58] | 92 | {
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[41924f30] | 93 | atomic_inc(&ep->refcnt);
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[f527f58] | 94 | }
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| 95 |
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[1102eca] | 96 | /**
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| 97 | * Call the desctruction callback. Default behavior is to free the memory directly.
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| 98 | */
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[6832245] | 99 | static inline void endpoint_destroy(endpoint_t *ep)
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| 100 | {
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[296d22fc] | 101 | const bus_ops_t *ops = get_bus_ops(ep);
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| 102 | if (ops->endpoint_destroy) {
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[6832245] | 103 | ops->endpoint_destroy(ep);
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| 104 | } else {
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| 105 | assert(ep->active_batch == NULL);
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| 106 |
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| 107 | /* Assume mostly the eps will be allocated by malloc. */
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| 108 | free(ep);
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| 109 | }
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| 110 | }
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| 111 |
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[1102eca] | 112 | /**
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| 113 | * Decrease the reference count.
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| 114 | */
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[41924f30] | 115 | void endpoint_del_ref(endpoint_t *ep)
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[f527f58] | 116 | {
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[41924f30] | 117 | if (atomic_predec(&ep->refcnt) == 0) {
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[6832245] | 118 | endpoint_destroy(ep);
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[41924f30] | 119 | }
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[3d932af6] | 120 | }
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[a76b01b4] | 121 |
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[0892663a] | 122 | /**
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[4db49344] | 123 | * Mark the endpoint as online. Supply a guard to be used for this endpoint
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| 124 | * synchronization.
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| 125 | */
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| 126 | void endpoint_set_online(endpoint_t *ep, fibril_mutex_t *guard)
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| 127 | {
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| 128 | ep->guard = guard;
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| 129 | ep->online = true;
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| 130 | }
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| 131 |
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| 132 | /**
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| 133 | * Mark the endpoint as offline. All other fibrils waiting to activate this
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| 134 | * endpoint will be interrupted.
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| 135 | */
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| 136 | void endpoint_set_offline_locked(endpoint_t *ep)
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| 137 | {
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| 138 | assert(ep);
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| 139 | assert(fibril_mutex_is_locked(ep->guard));
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| 140 |
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| 141 | ep->online = false;
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| 142 | fibril_condvar_broadcast(&ep->avail);
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| 143 | }
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| 144 |
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| 145 | /**
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| 146 | * Wait until a transfer finishes. Can be used even when the endpoint is
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| 147 | * offline (and is interrupted by the endpoint going offline).
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[0892663a] | 148 | */
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| 149 | void endpoint_wait_timeout_locked(endpoint_t *ep, suseconds_t timeout)
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| 150 | {
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[4db49344] | 151 | assert(ep);
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| 152 | assert(fibril_mutex_is_locked(ep->guard));
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[0892663a] | 153 |
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[4db49344] | 154 | if (ep->active_batch == NULL)
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| 155 | return;
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[92caadd] | 156 |
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[4db49344] | 157 | fibril_condvar_wait_timeout(&ep->avail, ep->guard, timeout);
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[0892663a] | 158 | }
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| 159 |
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[1102eca] | 160 | /**
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| 161 | * Mark the endpoint as active and block access for further fibrils. If the
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| 162 | * endpoint is already active, it will block on ep->avail condvar.
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| 163 | *
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| 164 | * Call only under endpoint guard. After you activate the endpoint and release
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[4db49344] | 165 | * the guard, you must assume that particular transfer is already
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| 166 | * finished/aborted.
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| 167 | *
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| 168 | * Activation and deactivation is not done by the library to maximize
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| 169 | * performance. The HC might want to prepare some memory buffers prior to
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| 170 | * interfering with other world.
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[1102eca] | 171 | *
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[4db49344] | 172 | * @param batch Transfer batch this endpoint is blocked by.
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[17412546] | 173 | */
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[4db49344] | 174 | int endpoint_activate_locked(endpoint_t *ep, usb_transfer_batch_t *batch)
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[6a32665d] | 175 | {
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[41924f30] | 176 | assert(ep);
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[17873ac7] | 177 | assert(batch);
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| 178 | assert(batch->ep == ep);
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[4db49344] | 179 | assert(ep->guard);
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| 180 | assert(fibril_mutex_is_locked(ep->guard));
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[17873ac7] | 181 |
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[4db49344] | 182 | while (ep->online && ep->active_batch != NULL)
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| 183 | fibril_condvar_wait(&ep->avail, ep->guard);
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| 184 |
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| 185 | if (!ep->online)
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| 186 | return EINTR;
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| 187 |
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| 188 | assert(ep->active_batch == NULL);
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[17873ac7] | 189 | ep->active_batch = batch;
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[4db49344] | 190 | return EOK;
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[6a32665d] | 191 | }
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[a76b01b4] | 192 |
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[1102eca] | 193 | /**
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| 194 | * Mark the endpoint as inactive and allow access for further fibrils.
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[17412546] | 195 | */
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[17873ac7] | 196 | void endpoint_deactivate_locked(endpoint_t *ep)
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[6a32665d] | 197 | {
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[41924f30] | 198 | assert(ep);
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[4db49344] | 199 | assert(fibril_mutex_is_locked(ep->guard));
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| 200 |
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[17873ac7] | 201 | ep->active_batch = NULL;
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| 202 | fibril_condvar_signal(&ep->avail);
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| 203 | }
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| 204 |
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[1102eca] | 205 | /**
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| 206 | * Initiate a transfer on an endpoint. Creates a transfer batch, checks the
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| 207 | * bandwidth requirements and schedules the batch.
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| 208 | *
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| 209 | * @param endpoint Endpoint for which to send the batch
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[32fb6bce] | 210 | */
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[1d758fc] | 211 | errno_t endpoint_send_batch(endpoint_t *ep, const transfer_request_t *req)
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[32fb6bce] | 212 | {
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[1d758fc] | 213 | assert(ep);
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| 214 | assert(req);
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[defaab2] | 215 |
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| 216 | if (ep->transfer_type == USB_TRANSFER_CONTROL) {
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[1d758fc] | 217 | usb_log_debug("%s %d:%d %zu/%zuB, setup %#016" PRIx64, req->name,
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| 218 | req->target.address, req->target.endpoint,
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| 219 | req->size, ep->max_packet_size,
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| 220 | req->setup);
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[defaab2] | 221 | } else {
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[1d758fc] | 222 | usb_log_debug("%s %d:%d %zu/%zuB", req->name,
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| 223 | req->target.address, req->target.endpoint,
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| 224 | req->size, ep->max_packet_size);
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[defaab2] | 225 | }
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[32fb6bce] | 226 |
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[3bacee1] | 227 | device_t *const device = ep->device;
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[9748336] | 228 | if (!device) {
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| 229 | usb_log_warning("Endpoint detached");
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| 230 | return EAGAIN;
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| 231 | }
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| 232 |
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[296d22fc] | 233 | const bus_ops_t *ops = device->bus->ops;
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| 234 | if (!ops->batch_schedule) {
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[a1732929] | 235 | usb_log_error("HCD does not implement scheduler.");
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[32fb6bce] | 236 | return ENOTSUP;
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| 237 | }
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| 238 |
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[1d758fc] | 239 | size_t size = req->size;
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[af16ebe] | 240 | /*
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| 241 | * Limit transfers with reserved bandwidth to the amount reserved.
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| 242 | * OUT transfers are rejected, IN can be just trimmed in advance.
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| 243 | */
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[1d758fc] | 244 | if (size > ep->max_transfer_size &&
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[3bacee1] | 245 | (ep->transfer_type == USB_TRANSFER_INTERRUPT ||
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| 246 | ep->transfer_type == USB_TRANSFER_ISOCHRONOUS)) {
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[1d758fc] | 247 | if (req->dir == USB_DIRECTION_OUT)
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[af16ebe] | 248 | return ENOSPC;
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| 249 | else
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| 250 | size = ep->max_transfer_size;
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| 251 | }
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[5f0b366] | 252 |
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[deb2e55] | 253 | /* Offline devices don't schedule transfers other than on EP0. */
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[5f0b366] | 254 | if (!device->online && ep->endpoint > 0)
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[deb2e55] | 255 | return EAGAIN;
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[32fb6bce] | 256 |
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| 257 | usb_transfer_batch_t *batch = usb_transfer_batch_create(ep);
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| 258 | if (!batch) {
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[a1732929] | 259 | usb_log_error("Failed to create transfer batch.");
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[32fb6bce] | 260 | return ENOMEM;
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| 261 | }
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| 262 |
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[1d758fc] | 263 | batch->target = req->target;
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| 264 | batch->setup.packed = req->setup;
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| 265 | batch->dir = req->dir;
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| 266 | batch->size = size;
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| 267 | batch->offset = req->offset;
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| 268 | batch->dma_buffer = req->buffer;
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[c21e6a5] | 269 |
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[1d758fc] | 270 | dma_buffer_acquire(&batch->dma_buffer);
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| 271 |
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| 272 | if (batch->offset != 0) {
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| 273 | usb_log_debug("A transfer with nonzero offset requested.");
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| 274 | usb_transfer_batch_bounce(batch);
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[c21e6a5] | 275 | }
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| 276 |
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[1d758fc] | 277 | if (usb_transfer_batch_bounce_required(batch))
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| 278 | usb_transfer_batch_bounce(batch);
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| 279 |
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| 280 | batch->on_complete = req->on_complete;
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| 281 | batch->on_complete_data = req->arg;
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[32fb6bce] | 282 |
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| 283 | const int ret = ops->batch_schedule(batch);
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| 284 | if (ret != EOK) {
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| 285 | usb_log_warning("Batch %p failed to schedule: %s", batch, str_error(ret));
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| 286 | usb_transfer_batch_destroy(batch);
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| 287 | }
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| 288 |
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| 289 | return ret;
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| 290 | }
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| 291 |
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[6ce42e85] | 292 | /**
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| 293 | * @}
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| 294 | */
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