[6ce42e85] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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[41924f30] | 3 | * Copyright (c) 2017 Ondrej Hlavaty <aearsis@eideo.cz>
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[6ce42e85] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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[f527f58] | 29 |
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[17412546] | 30 | /** @addtogroup libusbhost
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[6ce42e85] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | * @brief UHCI host controller driver structure
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| 35 | */
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| 36 |
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[6a32665d] | 37 | #include <assert.h>
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[f527f58] | 38 | #include <atomic.h>
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[41924f30] | 39 | #include <mem.h>
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| 40 | #include <stdlib.h>
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[32fb6bce] | 41 | #include <str_error.h>
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| 42 | #include <usb/debug.h>
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[9efad54] | 43 | #include <usb/descriptor.h>
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[32fb6bce] | 44 | #include <usb/host/hcd.h>
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[6ce42e85] | 45 |
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[64fea02] | 46 | #include "usb_transfer_batch.h"
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| 47 | #include "bus.h"
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| 48 |
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| 49 | #include "endpoint.h"
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| 50 |
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[1102eca] | 51 | /**
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| 52 | * Initialize provided endpoint structure.
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[17412546] | 53 | */
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[9efad54] | 54 | void endpoint_init(endpoint_t *ep, device_t *dev, const usb_endpoint_descriptors_t *desc)
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[6ce42e85] | 55 | {
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[41924f30] | 56 | memset(ep, 0, sizeof(endpoint_t));
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[a76b01b4] | 57 |
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[6832245] | 58 | assert(dev);
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| 59 | ep->device = dev;
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| 60 |
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[41924f30] | 61 | atomic_set(&ep->refcnt, 0);
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| 62 | link_initialize(&ep->link);
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| 63 | fibril_mutex_initialize(&ep->guard);
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| 64 | fibril_condvar_initialize(&ep->avail);
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[6832245] | 65 |
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[9efad54] | 66 | ep->endpoint = USB_ED_GET_EP(desc->endpoint);
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| 67 | ep->direction = USB_ED_GET_DIR(desc->endpoint);
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| 68 | ep->transfer_type = USB_ED_GET_TRANSFER_TYPE(desc->endpoint);
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| 69 | ep->max_packet_size = USB_ED_GET_MPS(desc->endpoint);
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| 70 | ep->packets_per_uframe = USB_ED_GET_ADD_OPPS(desc->endpoint) + 1;
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[6832245] | 71 |
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[9efad54] | 72 | /** Direction both is our construct never present in descriptors */
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| 73 | if (ep->transfer_type == USB_TRANSFER_CONTROL)
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| 74 | ep->direction = USB_DIRECTION_BOTH;
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| 75 |
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| 76 | ep->max_transfer_size = ep->max_packet_size * ep->packets_per_uframe;
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| 77 |
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| 78 | ep->bandwidth = endpoint_count_bw(ep, ep->max_transfer_size);
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[6832245] | 79 | }
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| 80 |
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[1102eca] | 81 | /**
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| 82 | * Get the bus endpoint belongs to.
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| 83 | */
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[6832245] | 84 | static inline const bus_ops_t *get_bus_ops(endpoint_t *ep)
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| 85 | {
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| 86 | return ep->device->bus->ops;
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[6ce42e85] | 87 | }
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[a76b01b4] | 88 |
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[1102eca] | 89 | /**
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| 90 | * Increase the reference count on endpoint.
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| 91 | */
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[41924f30] | 92 | void endpoint_add_ref(endpoint_t *ep)
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[f527f58] | 93 | {
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[41924f30] | 94 | atomic_inc(&ep->refcnt);
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[f527f58] | 95 | }
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| 96 |
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[1102eca] | 97 | /**
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| 98 | * Call the desctruction callback. Default behavior is to free the memory directly.
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| 99 | */
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[6832245] | 100 | static inline void endpoint_destroy(endpoint_t *ep)
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| 101 | {
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| 102 | const bus_ops_t *ops = BUS_OPS_LOOKUP(get_bus_ops(ep), endpoint_destroy);
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| 103 | if (ops) {
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| 104 | ops->endpoint_destroy(ep);
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| 105 | } else {
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| 106 | assert(ep->active_batch == NULL);
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| 107 |
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| 108 | /* Assume mostly the eps will be allocated by malloc. */
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| 109 | free(ep);
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| 110 | }
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| 111 | }
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| 112 |
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[1102eca] | 113 | /**
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| 114 | * Decrease the reference count.
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| 115 | */
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[41924f30] | 116 | void endpoint_del_ref(endpoint_t *ep)
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[f527f58] | 117 | {
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[41924f30] | 118 | if (atomic_predec(&ep->refcnt) == 0) {
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[6832245] | 119 | endpoint_destroy(ep);
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[41924f30] | 120 | }
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[3d932af6] | 121 | }
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[a76b01b4] | 122 |
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[56257ba] | 123 | static void endpoint_toggle_reset(endpoint_t *ep, toggle_reset_mode_t mode);
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| 124 |
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[0892663a] | 125 | /**
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| 126 | * Wait until the endpoint have no transfer scheduled.
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| 127 | */
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| 128 | void endpoint_wait_timeout_locked(endpoint_t *ep, suseconds_t timeout)
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| 129 | {
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| 130 | assert(fibril_mutex_is_locked(&ep->guard));
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| 131 |
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[92caadd] | 132 | if (ep->active_batch != NULL)
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| 133 | fibril_condvar_wait_timeout(&ep->avail, &ep->guard, timeout);
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| 134 |
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| 135 | while (timeout == 0 && ep->active_batch != NULL)
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[0892663a] | 136 | fibril_condvar_wait_timeout(&ep->avail, &ep->guard, timeout);
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| 137 | }
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| 138 |
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[1102eca] | 139 | /**
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| 140 | * Mark the endpoint as active and block access for further fibrils. If the
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| 141 | * endpoint is already active, it will block on ep->avail condvar.
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| 142 | *
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| 143 | * Call only under endpoint guard. After you activate the endpoint and release
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| 144 | * the guard, you must assume that particular transfer is already finished/aborted.
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| 145 | *
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[41924f30] | 146 | * @param ep endpoint_t structure.
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[1102eca] | 147 | * @param batch Transfer batch this endpoint is bocked by.
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[17412546] | 148 | */
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[17873ac7] | 149 | void endpoint_activate_locked(endpoint_t *ep, usb_transfer_batch_t *batch)
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[6a32665d] | 150 | {
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[41924f30] | 151 | assert(ep);
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[17873ac7] | 152 | assert(batch);
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| 153 | assert(batch->ep == ep);
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| 154 |
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[0892663a] | 155 | endpoint_wait_timeout_locked(ep, 0);
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[17873ac7] | 156 | ep->active_batch = batch;
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[6a32665d] | 157 | }
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[a76b01b4] | 158 |
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[1102eca] | 159 | /**
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| 160 | * Mark the endpoint as inactive and allow access for further fibrils.
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| 161 | *
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[41924f30] | 162 | * @param ep endpoint_t structure.
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[17412546] | 163 | */
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[17873ac7] | 164 | void endpoint_deactivate_locked(endpoint_t *ep)
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[6a32665d] | 165 | {
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[41924f30] | 166 | assert(ep);
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[17873ac7] | 167 | assert(fibril_mutex_is_locked(&ep->guard));
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| 168 |
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| 169 | if (ep->active_batch && ep->active_batch->error == EOK)
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[56257ba] | 170 | endpoint_toggle_reset(ep, ep->active_batch->toggle_reset_mode);
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[17873ac7] | 171 |
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| 172 | ep->active_batch = NULL;
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| 173 | fibril_condvar_signal(&ep->avail);
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| 174 | }
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| 175 |
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[1102eca] | 176 | /**
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| 177 | * The transfer on an endpoint can trigger a reset of the toggle bit. This
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| 178 | * function calls the respective bus callbacks to resolve it.
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| 179 | *
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| 180 | * @param ep The endpoint that triggered the reset
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| 181 | * @param mode Whether to reset no, one or all endpoints on a device.
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| 182 | */
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[56257ba] | 183 | static void endpoint_toggle_reset(endpoint_t *ep, toggle_reset_mode_t mode)
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[f567bcf] | 184 | {
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[41924f30] | 185 | assert(ep);
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[17873ac7] | 186 |
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[56257ba] | 187 | if (mode == RESET_NONE)
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| 188 | return;
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[a76b01b4] | 189 |
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[56257ba] | 190 | const bus_ops_t *ops = BUS_OPS_LOOKUP(get_bus_ops(ep), endpoint_toggle_reset);
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| 191 | if (!ops)
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| 192 | return;
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[17873ac7] | 193 |
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[56257ba] | 194 |
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| 195 | if (mode == RESET_ALL) {
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[1102eca] | 196 | const device_t *dev = ep->device;
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[56257ba] | 197 | for (usb_endpoint_t i = 0; i < USB_ENDPOINT_MAX; ++i) {
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| 198 | if (dev->endpoints[i])
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| 199 | ops->endpoint_toggle_reset(dev->endpoints[i]);
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| 200 | }
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| 201 | } else {
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| 202 | ops->endpoint_toggle_reset(ep);
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[41924f30] | 203 | }
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[f567bcf] | 204 | }
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[f527f58] | 205 |
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[1102eca] | 206 | /**
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| 207 | * Call the bus operation to count bandwidth.
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| 208 | *
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| 209 | * @param ep Endpoint on which the transfer will take place.
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| 210 | * @param size The payload size.
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| 211 | */
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| 212 | ssize_t endpoint_count_bw(endpoint_t *ep, size_t size)
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[6832245] | 213 | {
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| 214 | assert(ep);
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| 215 |
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| 216 | const bus_ops_t *ops = BUS_OPS_LOOKUP(get_bus_ops(ep), endpoint_count_bw);
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| 217 | if (!ops)
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| 218 | return 0;
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| 219 |
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[1102eca] | 220 | return ops->endpoint_count_bw(ep, size);
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[6832245] | 221 | }
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| 222 |
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[1102eca] | 223 | /**
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| 224 | * Initiate a transfer on an endpoint. Creates a transfer batch, checks the
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| 225 | * bandwidth requirements and schedules the batch.
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| 226 | *
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| 227 | * @param endpoint Endpoint for which to send the batch
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| 228 | * @param target The target of the transfer.
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| 229 | * @param direction A direction of the transfer.
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| 230 | * @param data A pointer to the data buffer.
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| 231 | * @param size Size of the data buffer.
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| 232 | * @param setup_data Data to use in the setup stage (Control communication type)
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| 233 | * @param on_complete Callback which is called after the batch is complete
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[32fb6bce] | 234 | * @param arg Callback parameter.
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| 235 | * @param name Communication identifier (for nicer output).
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| 236 | */
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| 237 | int endpoint_send_batch(endpoint_t *ep, usb_target_t target,
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| 238 | usb_direction_t direction, char *data, size_t size, uint64_t setup_data,
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| 239 | usbhc_iface_transfer_callback_t on_complete, void *arg, const char *name)
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| 240 | {
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[a1732929] | 241 | usb_log_debug2("%s %d:%d %zu(%zu).",
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[32fb6bce] | 242 | name, target.address, target.endpoint, size, ep->max_packet_size);
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| 243 |
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[9748336] | 244 | device_t * const device = ep->device;
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| 245 | if (!device) {
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| 246 | usb_log_warning("Endpoint detached");
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| 247 | return EAGAIN;
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| 248 | }
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| 249 |
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| 250 | const bus_ops_t *ops = BUS_OPS_LOOKUP(device->bus->ops, batch_schedule);
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[32fb6bce] | 251 | if (!ops) {
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[a1732929] | 252 | usb_log_error("HCD does not implement scheduler.");
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[32fb6bce] | 253 | return ENOTSUP;
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| 254 | }
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| 255 |
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[deb2e55] | 256 | /* Offline devices don't schedule transfers other than on EP0. */
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[9748336] | 257 | if (!device->online && ep->endpoint > 0) {
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[deb2e55] | 258 | return EAGAIN;
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| 259 | }
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| 260 |
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[32fb6bce] | 261 | const size_t bw = endpoint_count_bw(ep, size);
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| 262 | /* Check if we have enough bandwidth reserved */
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| 263 | if (ep->bandwidth < bw) {
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| 264 | usb_log_error("Endpoint(%d:%d) %s needs %zu bw "
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| 265 | "but only %zu is reserved.\n",
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[9748336] | 266 | device->address, ep->endpoint, name, bw, ep->bandwidth);
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[32fb6bce] | 267 | return ENOSPC;
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| 268 | }
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| 269 |
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| 270 | usb_transfer_batch_t *batch = usb_transfer_batch_create(ep);
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| 271 | if (!batch) {
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[a1732929] | 272 | usb_log_error("Failed to create transfer batch.");
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[32fb6bce] | 273 | return ENOMEM;
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| 274 | }
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| 275 |
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| 276 | batch->target = target;
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| 277 | batch->buffer = data;
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| 278 | batch->buffer_size = size;
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| 279 | batch->setup.packed = setup_data;
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| 280 | batch->dir = direction;
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| 281 | batch->on_complete = on_complete;
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| 282 | batch->on_complete_data = arg;
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| 283 |
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| 284 | /* Check for commands that reset toggle bit */
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| 285 | if (ep->transfer_type == USB_TRANSFER_CONTROL)
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| 286 | batch->toggle_reset_mode
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| 287 | = hcd_get_request_toggle_reset_mode(&batch->setup.packet);
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| 288 |
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| 289 | const int ret = ops->batch_schedule(batch);
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| 290 | if (ret != EOK) {
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| 291 | usb_log_warning("Batch %p failed to schedule: %s", batch, str_error(ret));
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| 292 | usb_transfer_batch_destroy(batch);
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| 293 | }
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| 294 |
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| 295 | return ret;
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| 296 | }
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| 297 |
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[6ce42e85] | 298 | /**
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| 299 | * @}
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| 300 | */
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