source: mainline/uspace/lib/libc/arch/mips32/include/thread.h@ 5d4e90f0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5d4e90f0 was bc1f1c2, checked in by Jakub Jermar <jakub@…>, 18 years ago

Goodbye pseudo threads, welcome fibrils.
The renaming might still be incomplete.

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 * Copyright (c) 2006 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup libcmips32
30 * @{
31 */
32/** @file
33 * @ingroup libcmips32eb
34 */
35
36/* TLS for MIPS is described in http://www.linux-mips.org/wiki/NPTL */
37
38#ifndef LIBC_mips32_THREAD_H_
39#define LIBC_mips32_THREAD_H_
40
41/* I did not find any specification (neither MIPS nor PowerPC), but
42 * as I found it
43 * - it uses Variant II
44 * - TCB is at Address(First TLS Block)+0x7000.
45 * - DTV is at Address(First TLS Block)+0x8000
46 * - What would happen if the TLS data was larger then 0x7000?
47 * - The linker never accesses DTV directly, has the second definition any
48 * sense?
49 * We will make it this way:
50 * - TCB is at TP-0x7000-sizeof(tcb)
51 * - No assumption about DTV etc., but it will not have a fixed address
52 */
53#define MIPS_TP_OFFSET 0x7000
54
55typedef struct {
56 void *fibril_data;
57} tcb_t;
58
59static inline void __tcb_set(tcb_t *tcb)
60{
61 void *tp = tcb;
62 tp += MIPS_TP_OFFSET + sizeof(tcb_t);
63
64 asm volatile ("add $27, %0, $0" : : "r"(tp)); /* Move tls to K1 */
65}
66
67static inline tcb_t * __tcb_get(void)
68{
69 void * retval;
70
71 asm volatile("add %0, $27, $0" : "=r"(retval));
72
73 return (tcb_t *)(retval - MIPS_TP_OFFSET - sizeof(tcb_t));
74}
75
76#endif
77
78/** @}
79 */
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