source: mainline/uspace/lib/libc/arch/mips32/include/atomic.h@ d2bdd245

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d2bdd245 was d2bdd245, checked in by Jiri Svoboda <jirik.svoboda@…>, 17 years ago

Fix register constraints in mips32 libc atomic_add()

  • Property mode set to 100644
File size: 2.5 KB
RevLine 
[7e2988c]1/*
[df4ed85]2 * Copyright (c) 2005 Ondrej Palkovsky
[7e2988c]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[fadd381]29/** @addtogroup libcmips32
[e209fc96]30 * @{
31 */
32/** @file
[846848a6]33 * @ingroup libcmips32eb
[e209fc96]34 */
35
[fadd381]36#ifndef LIBC_mips32_ATOMIC_H_
37#define LIBC_mips32_ATOMIC_H_
[7e2988c]38
39#define atomic_inc(x) ((void) atomic_add(x, 1))
40#define atomic_dec(x) ((void) atomic_add(x, -1))
41
42#define atomic_postinc(x) (atomic_add(x, 1) - 1)
43#define atomic_postdec(x) (atomic_add(x, -1) + 1)
44
45#define atomic_preinc(x) atomic_add(x, 1)
46#define atomic_predec(x) atomic_add(x, -1)
47
48/* Atomic addition of immediate value.
49 *
50 * @param val Memory location to which will be the immediate value added.
51 * @param i Signed immediate that will be added to *val.
52 *
53 * @return Value after addition.
54 */
55static inline long atomic_add(atomic_t *val, int i)
56{
57 long tmp, v;
58
[e7b7be3f]59 asm volatile (
[7e2988c]60 "1:\n"
61 " ll %0, %1\n"
62 " addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */
63 " move %2, %0\n"
64 " sc %0, %1\n"
65 " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
66 /* nop */ /* nop is inserted automatically by compiler */
[d2bdd245]67 : "=&r" (tmp), "=m" (val->count), "=&r" (v)
[7e2988c]68 : "i" (i), "i" (0)
69 );
70
71 return v;
72}
73
74#endif
[e209fc96]75
[fadd381]76/** @}
[e209fc96]77 */
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