source: mainline/uspace/lib/libc/arch/ia64/include/atomic.h@ 4702bde

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4702bde was e86a849a, checked in by Martin Decky <martin@…>, 16 years ago

use fetchadd8.rel directly, not via atomic_add()
(3rd operand of fetchadd8.rel cannot be an arbitrary integer, only ± 1, 4, 8 or 16, thus the "i" constraint is not enought)

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup libcia64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef LIBC_ia64_ATOMIC_H_
36#define LIBC_ia64_ATOMIC_H_
37
38static inline void atomic_inc(atomic_t *val)
39{
40 long v;
41
42 asm volatile (
43 "fetchadd8.rel %[v] = %[count], 1\n"
44 : [v] "=r" (v),
45 [count] "+m" (val->count)
46 );
47}
48
49static inline void atomic_dec(atomic_t *val)
50{
51 long v;
52
53 asm volatile (
54 "fetchadd8.rel %[v] = %[count], -1\n"
55 : [v] "=r" (v),
56 [count] "+m" (val->count)
57 );
58}
59
60static inline long atomic_preinc(atomic_t *val)
61{
62 long v;
63
64 asm volatile (
65 "fetchadd8.rel %[v] = %[count], 1\n"
66 : [v] "=r" (v),
67 [count] "+m" (val->count)
68 );
69
70 return (v + 1);
71}
72
73static inline long atomic_predec(atomic_t *val)
74{
75 long v;
76
77 asm volatile (
78 "fetchadd8.rel %[v] = %[count], -1\n"
79 : [v] "=r" (v),
80 [count] "+m" (val->count)
81 );
82
83 return (v - 1);
84}
85
86static inline long atomic_postinc(atomic_t *val)
87{
88 long v;
89
90 asm volatile (
91 "fetchadd8.rel %[v] = %[count], 1\n"
92 : [v] "=r" (v),
93 [count] "+m" (val->count)
94 );
95
96 return v;
97}
98
99static inline long atomic_postdec(atomic_t *val)
100{
101 long v;
102
103 asm volatile (
104 "fetchadd8.rel %[v] = %[count], -1\n"
105 : [v] "=r" (v),
106 [count] "+m" (val->count)
107 );
108
109 return v;
110}
111
112#endif
113
114/** @}
115 */
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