source: mainline/uspace/lib/libc/arch/arm32/include/atomic.h@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was cd769305, checked in by Jakub Jermar <jakub@…>, 16 years ago

Implement userspace arm32 cas() and atomic_add() using RAS.

  • Property mode set to 100644
File size: 4.4 KB
RevLine 
[d630139]1/*
[6b781c0]2 * Copyright (c) 2007 Michal Kebrt
[d630139]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup libcarm32
30 * @{
31 */
32/** @file
[6b781c0]33 * @brief Atomic operations.
[d630139]34 */
35
36#ifndef LIBC_arm32_ATOMIC_H_
37#define LIBC_arm32_ATOMIC_H_
38
[cd769305]39#define LIBC_ARCH_ATOMIC_H_
40#define CAS
41
42#include <atomicdflt.h>
[8d04f709]43#include <bool.h>
[cd769305]44#include <sys/types.h>
[8d04f709]45
[cd769305]46extern uintptr_t *ras_page;
[8d04f709]47
[cd769305]48static inline bool cas(atomic_t *val, long ov, long nv)
[8d04f709]49{
[cd769305]50 long ret = 0;
[8d04f709]51
[cd769305]52 /*
53 * The following instructions between labels 1 and 2 constitute a
54 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
55 * the kernel will restart it.
56 */
57 asm volatile (
58 "1:\n"
59 " adr %[ret], 1b\n"
60 " str %[ret], %[rp0]\n"
61 " adr %[ret], 2f\n"
62 " str %[ret], %[rp1]\n"
63 " ldr %[ret], %[addr]\n"
64 " cmp %[ret], %[ov]\n"
65 " streq %[nv], %[addr]\n"
66 "2:\n"
67 " moveq %[ret], #1\n"
68 " movne %[ret], #0\n"
69 : [ret] "+&r" (ret),
70 [rp0] "=m" (ras_page[0]),
71 [rp1] "=m" (ras_page[1]),
72 [addr] "+m" (val->count)
73 : [ov] "r" (ov),
74 [nv] "r" (nv)
75 : "memory"
76 );
[8d04f709]77
[cd769305]78 ras_page[0] = 0;
79 asm volatile ("" ::: "memory");
80 ras_page[1] = 0xffffffff;
81
82 return (bool) ret;
[8d04f709]83}
84
[d630139]85/** Atomic addition.
86 *
[6b781c0]87 * @param val Where to add.
88 * @param i Value to be added.
[d630139]89 *
90 * @return Value after addition.
91 */
[6b781c0]92static inline long atomic_add(atomic_t *val, int i)
[d630139]93{
[cd769305]94 long ret = 0;
[6b781c0]95
[cd769305]96 /*
97 * The following instructions between labels 1 and 2 constitute a
98 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
99 * the kernel will restart it.
100 */
[6b781c0]101 asm volatile (
[cd769305]102 "1:\n"
103 " adr %[ret], 1b\n"
104 " str %[ret], %[rp0]\n"
105 " adr %[ret], 2f\n"
106 " str %[ret], %[rp1]\n"
107 " ldr %[ret], %[addr]\n"
108 " add %[ret], %[ret], %[imm]\n"
109 " str %[ret], %[addr]\n"
110 "2:\n"
111 : [ret] "+&r" (ret),
112 [rp0] "=m" (ras_page[0]),
113 [rp1] "=m" (ras_page[1]),
114 [addr] "+m" (val->count)
115 : [imm] "r" (i)
[6b781c0]116 );
117
[cd769305]118 ras_page[0] = 0;
119 asm volatile ("" ::: "memory");
120 ras_page[1] = 0xffffffff;
121
[6b781c0]122 return ret;
[d630139]123}
124
[6b781c0]125
126/** Atomic increment.
127 *
128 * @param val Variable to be incremented.
129 */
[de7663f]130static inline void atomic_inc(atomic_t *val)
131{
132 atomic_add(val, 1);
133}
[6b781c0]134
135
136/** Atomic decrement.
137 *
138 * @param val Variable to be decremented.
139 */
[de7663f]140static inline void atomic_dec(atomic_t *val)
141{
142 atomic_add(val, -1);
143}
[d630139]144
145
[6b781c0]146/** Atomic pre-increment.
147 *
148 * @param val Variable to be incremented.
149 * @return Value after incrementation.
150 */
[de7663f]151static inline long atomic_preinc(atomic_t *val)
152{
153 return atomic_add(val, 1);
154}
[6b781c0]155
156
157/** Atomic pre-decrement.
158 *
159 * @param val Variable to be decremented.
160 * @return Value after decrementation.
161 */
[de7663f]162static inline long atomic_predec(atomic_t *val)
163{
164 return atomic_add(val, -1);
165}
[6b781c0]166
167
168/** Atomic post-increment.
169 *
170 * @param val Variable to be incremented.
171 * @return Value before incrementation.
172 */
[de7663f]173static inline long atomic_postinc(atomic_t *val)
174{
175 return atomic_add(val, 1) - 1;
176}
[6b781c0]177
178
179/** Atomic post-decrement.
180 *
181 * @param val Variable to be decremented.
182 * @return Value before decrementation.
183 */
[de7663f]184static inline long atomic_postdec(atomic_t *val)
185{
186 return atomic_add(val, -1) + 1;
187}
[6b781c0]188
[d630139]189
190#endif
191
192/** @}
193 */
Note: See TracBrowser for help on using the repository browser.