source: mainline/uspace/lib/c/arch/sparc64/include/libarch/ddi.h@ 002fd5f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 002fd5f was 7ee7e6a, checked in by Jakub Jermar <jakub@…>, 8 years ago

Further reduce the number of inclusions of sys/types.h

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 * Copyright (c) 2009 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * @ingroup libsparc64
31 */
32
33#ifndef LIBC_sparc64_DDI_H_
34#define LIBC_sparc64_DDI_H_
35
36#include <ddi.h>
37
38static inline void memory_barrier(void)
39{
40 asm volatile (
41 "membar #LoadLoad | #StoreStore\n"
42 ::: "memory"
43 );
44}
45
46static inline void arch_pio_write_8(ioport8_t *port, uint8_t v)
47{
48 *port = v;
49 memory_barrier();
50}
51
52static inline void arch_pio_write_16(ioport16_t *port, uint16_t v)
53{
54 *port = v;
55 memory_barrier();
56}
57
58static inline void arch_pio_write_32(ioport32_t *port, uint32_t v)
59{
60 *port = v;
61 memory_barrier();
62}
63
64static inline uint8_t arch_pio_read_8(const ioport8_t *port)
65{
66 uint8_t rv;
67
68 rv = *port;
69 memory_barrier();
70
71 return rv;
72}
73
74static inline uint16_t arch_pio_read_16(const ioport16_t *port)
75{
76 uint16_t rv;
77
78 rv = *port;
79 memory_barrier();
80
81 return rv;
82}
83
84static inline uint32_t arch_pio_read_32(const ioport32_t *port)
85{
86 uint32_t rv;
87
88 rv = *port;
89 memory_barrier();
90
91 return rv;
92}
93
94#endif
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