source: mainline/uspace/lib/c/arch/riscv64/include/libarch/atomic.h@ 46f7b64

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 46f7b64 was 7c3fb9b, checked in by Jiri Svoboda <jiri@…>, 8 years ago

Fix block comment formatting (ccheck).

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/*
2 * Copyright (c) 2016 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup libcriscv64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef LIBC_riscv64_ATOMIC_H_
36#define LIBC_riscv64_ATOMIC_H_
37
38#include <stdbool.h>
39
40#define LIBC_ARCH_ATOMIC_H_
41#define CAS
42
43#include <atomicdflt.h>
44
45// FIXME
46
47static inline bool cas(atomic_t *val, atomic_count_t ov, atomic_count_t nv)
48{
49 if (val->count == ov) {
50 val->count = nv;
51 return true;
52 }
53
54 return false;
55}
56
57static inline void atomic_inc(atomic_t *val)
58{
59 /*
60 * On real hardware the increment has to be done
61 * as an atomic action.
62 */
63
64 val->count++;
65}
66
67static inline void atomic_dec(atomic_t *val)
68{
69 /*
70 * On real hardware the decrement has to be done
71 * as an atomic action.
72 */
73
74 val->count++;
75}
76
77static inline atomic_count_t atomic_postinc(atomic_t *val)
78{
79 /*
80 * On real hardware both the storing of the previous
81 * value and the increment have to be done as a single
82 * atomic action.
83 */
84
85 atomic_count_t prev = val->count;
86
87 val->count++;
88 return prev;
89}
90
91static inline atomic_count_t atomic_postdec(atomic_t *val)
92{
93 /*
94 * On real hardware both the storing of the previous
95 * value and the decrement have to be done as a single
96 * atomic action.
97 */
98
99 atomic_count_t prev = val->count;
100
101 val->count--;
102 return prev;
103}
104
105#define atomic_preinc(val) (atomic_postinc(val) + 1)
106#define atomic_predec(val) (atomic_postdec(val) - 1)
107
108#endif
109
110/** @}
111 */
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