source: mainline/uspace/lib/c/arch/mips32/src/syscall.c@ 27ba40f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 27ba40f was 27ba40f, checked in by Martin Decky <martin@…>, 14 years ago

cstyle (no change in functionality)

  • Property mode set to 100644
File size: 2.4 KB
RevLine 
[b861b58]1/*
[df4ed85]2 * Copyright (c) 2005 Martin Decky
[b861b58]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[27ba40f]29/** @addtogroup libcmips32
[e209fc96]30 * @{
31 */
32/** @file
[27ba40f]33 * @ingroup libcmips32
[e209fc96]34 */
35
[b861b58]36#include <libc.h>
37
[9c2fb97]38sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3,
39 const sysarg_t p4, const sysarg_t p5, const sysarg_t p6, const syscall_t id)
[b861b58]40{
[3a6d6656]41 register sysarg_t __mips_reg_a0 asm("$4") = p1;
42 register sysarg_t __mips_reg_a1 asm("$5") = p2;
43 register sysarg_t __mips_reg_a2 asm("$6") = p3;
[7fc78da]44 register sysarg_t __mips_reg_a3 asm("$7") = p4;
[9c2fb97]45 register sysarg_t __mips_reg_t0 asm("$8") = p5;
46 register sysarg_t __mips_reg_t1 asm("$9") = p6;
[29c1282]47 register sysarg_t __mips_reg_v0 asm("$2") = id;
[b861b58]48
49 asm volatile (
50 "syscall\n"
[cc6f688]51 : "=r" (__mips_reg_v0)
[b861b58]52 : "r" (__mips_reg_a0),
53 "r" (__mips_reg_a1),
54 "r" (__mips_reg_a2),
[7fc78da]55 "r" (__mips_reg_a3),
[9c2fb97]56 "r" (__mips_reg_t0),
57 "r" (__mips_reg_t1),
[29c1282]58 "r" (__mips_reg_v0)
[255ec35]59 : "%ra" /* We are a function call, although C does not
60 * know it */
[b861b58]61 );
[cc6f688]62
63 return __mips_reg_v0;
[b861b58]64}
[e209fc96]65
[27ba40f]66/** @}
[e209fc96]67 */
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