source: mainline/uspace/lib/c/arch/ia32/include/atomic.h@ bb74dabe

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since bb74dabe was c8f70eb, checked in by Petr Koupy <petr.koupy@…>, 14 years ago

pcc incompatible inline assembly rewritten in a more agreeable fashion.

  • Property mode set to 100644
File size: 2.7 KB
RevLine 
[7e2988c]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[7e2988c]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[fadd381]29/** @addtogroup libcia32
[e209fc96]30 * @{
31 */
32/** @file
33 */
34
[fadd381]35#ifndef LIBC_ia32_ATOMIC_H_
36#define LIBC_ia32_ATOMIC_H_
[7e2988c]37
[e15e0e8]38#define LIBC_ARCH_ATOMIC_H_
39
40#include <atomicdflt.h>
41
[228666c]42static inline void atomic_inc(atomic_t *val)
43{
[c8f70eb]44#ifdef __PCC__
[228666c]45 asm volatile (
[1e891d0]46 "lock incl %0\n"
47 : "+m" (val->count)
[228666c]48 );
[c8f70eb]49#else
50 asm volatile (
51 "lock incl %[count]\n"
52 : [count] "+m" (val->count)
53 );
54#endif
[7e2988c]55}
56
[228666c]57static inline void atomic_dec(atomic_t *val)
58{
[c8f70eb]59#ifdef __PCC__
[228666c]60 asm volatile (
[1e891d0]61 "lock decl %0\n"
62 : "+m" (val->count)
[228666c]63 );
[c8f70eb]64#else
65 asm volatile (
66 "lock decl %[count]\n"
67 : [count] "+m" (val->count)
68 );
69#endif
[7e2988c]70}
71
[228666c]72static inline atomic_count_t atomic_postinc(atomic_t *val)
[7e2988c]73{
[228666c]74 atomic_count_t r = 1;
75
[c8f70eb]76#ifdef __PCC__
[e7b7be3f]77 asm volatile (
[1e891d0]78 "lock xaddl %1, %0\n"
79 : "+m" (val->count),
80 "+r" (r)
[7e2988c]81 );
[c8f70eb]82#else
83 asm volatile (
84 "lock xaddl %[r], %[count]\n"
85 : [count] "+m" (val->count),
86 [r] "+r" (r)
87 );
88#endif
[228666c]89
[7e2988c]90 return r;
91}
92
[228666c]93static inline atomic_count_t atomic_postdec(atomic_t *val)
[7e2988c]94{
[228666c]95 atomic_count_t r = -1;
[7e2988c]96
[c8f70eb]97#ifdef __PCC__
[e7b7be3f]98 asm volatile (
[1e891d0]99 "lock xaddl %1, %0\n"
100 : "+m" (val->count),
101 "+r" (r)
[7e2988c]102 );
[c8f70eb]103#else
104 asm volatile (
105 "lock xaddl %[r], %[count]\n"
106 : [count] "+m" (val->count),
107 [r] "+r" (r)
108 );
109#endif
[7e2988c]110
111 return r;
112}
113
[228666c]114#define atomic_preinc(val) (atomic_postinc(val) + 1)
115#define atomic_predec(val) (atomic_postdec(val) - 1)
[7e2988c]116
117#endif
[e209fc96]118
[fadd381]119/** @}
[e209fc96]120 */
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