source: mainline/uspace/lib/c/arch/arm32/src/atomic.c@ 6a57b93

Last change on this file since 6a57b93 was 56210a7a, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 11 months ago

Update GCC and binutils to latest versions
  • Property mode set to 100644
File size: 7.5 KB
Line 
1/*
2 * Copyright (c) 2007 Michal Kebrt
3 * Copyright (c) 2018 CZ.NIC, z.s.p.o.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * Older ARMs don't have atomic instructions, so we need to define a bunch
32 * of symbols for GCC to use.
33 */
34
35#include <stdbool.h>
36#include "ras_page.h"
37
38volatile unsigned *ras_page;
39
40bool __atomic_compare_exchange_4(volatile void *mem0, void *expected0,
41 unsigned desired, bool weak, int success, int failure)
42{
43 volatile unsigned *mem = mem0;
44 unsigned *expected = expected0;
45
46 (void) success;
47 (void) failure;
48 (void) weak;
49
50 unsigned ov = *expected;
51 unsigned ret;
52
53 /*
54 * The following instructions between labels 1 and 2 constitute a
55 * Restartable Atomic Sequence. Should the sequence be non-atomic,
56 * the kernel will restart it.
57 */
58 asm volatile (
59 "1:\n"
60 " adr %[ret], 1b\n"
61 " str %[ret], %[rp0]\n"
62 " adr %[ret], 2f\n"
63 " str %[ret], %[rp1]\n"
64
65 " ldr %[ret], %[addr]\n"
66 " cmp %[ret], %[ov]\n"
67 " streq %[nv], %[addr]\n"
68 "2:\n"
69 : [ret] "=&r" (ret),
70 [rp0] "=m" (ras_page[0]),
71 [rp1] "=m" (ras_page[1]),
72 [addr] "+m" (*mem)
73 : [ov] "r" (ov),
74 [nv] "r" (desired)
75 : "memory"
76 );
77
78 ras_page[0] = 0;
79 ras_page[1] = 0xffffffff;
80
81 if (ret == ov)
82 return true;
83
84 *expected = ret;
85 return false;
86}
87
88unsigned char __atomic_exchange_1(volatile void *mem0, unsigned char val,
89 int model)
90{
91 volatile unsigned char *mem = mem0;
92
93 (void) model;
94
95 unsigned ret;
96
97 /*
98 * The following instructions between labels 1 and 2 constitute a
99 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
100 * the kernel will restart it.
101 */
102 asm volatile (
103 "1:\n"
104 " adr %[ret], 1b\n"
105 " str %[ret], %[rp0]\n"
106 " adr %[ret], 2f\n"
107 " str %[ret], %[rp1]\n"
108 " ldrb %[ret], %[addr]\n"
109 " strb %[imm], %[addr]\n"
110 "2:\n"
111 : [ret] "=&r" (ret),
112 [rp0] "=m" (ras_page[0]),
113 [rp1] "=m" (ras_page[1]),
114 [addr] "+m" (*mem)
115 : [imm] "r" (val)
116 );
117
118 ras_page[0] = 0;
119 ras_page[1] = 0xffffffff;
120
121 return ret;
122}
123
124unsigned short __atomic_exchange_2(volatile void *mem0, unsigned short val,
125 int model)
126{
127 volatile unsigned short *mem = mem0;
128
129 (void) model;
130
131 unsigned ret;
132
133 /*
134 * The following instructions between labels 1 and 2 constitute a
135 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
136 * the kernel will restart it.
137 */
138 asm volatile (
139 "1:\n"
140 " adr %[ret], 1b\n"
141 " str %[ret], %[rp0]\n"
142 " adr %[ret], 2f\n"
143 " str %[ret], %[rp1]\n"
144 " ldrh %[ret], %[addr]\n"
145 " strh %[imm], %[addr]\n"
146 "2:\n"
147 : [ret] "=&r" (ret),
148 [rp0] "=m" (ras_page[0]),
149 [rp1] "=m" (ras_page[1]),
150 [addr] "+m" (*mem)
151 : [imm] "r" (val)
152 );
153
154 ras_page[0] = 0;
155 ras_page[1] = 0xffffffff;
156
157 return ret;
158}
159
160unsigned __atomic_exchange_4(volatile void *mem0, unsigned val, int model)
161{
162 volatile unsigned *mem = mem0;
163
164 (void) model;
165
166 unsigned ret;
167
168 /*
169 * The following instructions between labels 1 and 2 constitute a
170 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
171 * the kernel will restart it.
172 */
173 asm volatile (
174 "1:\n"
175 " adr %[ret], 1b\n"
176 " str %[ret], %[rp0]\n"
177 " adr %[ret], 2f\n"
178 " str %[ret], %[rp1]\n"
179 " ldr %[ret], %[addr]\n"
180 " str %[imm], %[addr]\n"
181 "2:\n"
182 : [ret] "=&r" (ret),
183 [rp0] "=m" (ras_page[0]),
184 [rp1] "=m" (ras_page[1]),
185 [addr] "+m" (*mem)
186 : [imm] "r" (val)
187 );
188
189 ras_page[0] = 0;
190 ras_page[1] = 0xffffffff;
191
192 return ret;
193}
194
195unsigned short __atomic_fetch_add_2(volatile void *mem0, unsigned short val,
196 int model)
197{
198 volatile unsigned short *mem = mem0;
199
200 (void) model;
201
202 unsigned short ret;
203
204 /*
205 * The following instructions between labels 1 and 2 constitute a
206 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
207 * the kernel will restart it.
208 */
209 asm volatile (
210 "1:\n"
211 " adr %[ret], 1b\n"
212 " str %[ret], %[rp0]\n"
213 " adr %[ret], 2f\n"
214 " str %[ret], %[rp1]\n"
215 " ldrh %[ret], %[addr]\n"
216 " add %[ret], %[ret], %[imm]\n"
217 " strh %[ret], %[addr]\n"
218 "2:\n"
219 : [ret] "=&r" (ret),
220 [rp0] "=m" (ras_page[0]),
221 [rp1] "=m" (ras_page[1]),
222 [addr] "+m" (*mem)
223 : [imm] "r" (val)
224 );
225
226 ras_page[0] = 0;
227 ras_page[1] = 0xffffffff;
228
229 return ret - val;
230}
231
232unsigned __atomic_fetch_add_4(volatile void *mem0, unsigned val, int model)
233{
234 volatile unsigned *mem = mem0;
235
236 (void) model;
237
238 unsigned ret;
239
240 /*
241 * The following instructions between labels 1 and 2 constitute a
242 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
243 * the kernel will restart it.
244 */
245 asm volatile (
246 "1:\n"
247 " adr %[ret], 1b\n"
248 " str %[ret], %[rp0]\n"
249 " adr %[ret], 2f\n"
250 " str %[ret], %[rp1]\n"
251 " ldr %[ret], %[addr]\n"
252 " add %[ret], %[ret], %[imm]\n"
253 " str %[ret], %[addr]\n"
254 "2:\n"
255 : [ret] "=&r" (ret),
256 [rp0] "=m" (ras_page[0]),
257 [rp1] "=m" (ras_page[1]),
258 [addr] "+m" (*mem)
259 : [imm] "r" (val)
260 );
261
262 ras_page[0] = 0;
263 ras_page[1] = 0xffffffff;
264
265 return ret - val;
266}
267
268unsigned __atomic_fetch_sub_4(volatile void *mem, unsigned val, int model)
269{
270 return __atomic_fetch_add_4(mem, -val, model);
271}
272
273bool __atomic_test_and_set(volatile void *ptr, int memorder)
274{
275 volatile unsigned char *b = ptr;
276
277 unsigned char orig = __atomic_exchange_n(b, (unsigned char) true, memorder);
278 return orig != 0;
279}
280
281void __sync_synchronize(void)
282{
283 // FIXME: Full memory barrier. We might need a syscall for this.
284}
285
286unsigned __sync_add_and_fetch_4(volatile void *vptr, unsigned val)
287{
288 return __atomic_fetch_add_4(vptr, val, __ATOMIC_SEQ_CST) + val;
289}
290
291unsigned __sync_sub_and_fetch_4(volatile void *vptr, unsigned val)
292{
293 return __atomic_fetch_sub_4(vptr, val, __ATOMIC_SEQ_CST) - val;
294}
295
296bool __sync_bool_compare_and_swap_4(volatile void *ptr, unsigned old_val, unsigned new_val)
297{
298 return __atomic_compare_exchange_4(ptr, &old_val, new_val, false,
299 __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
300}
301
302unsigned __sync_val_compare_and_swap_4(volatile void *ptr, unsigned old_val, unsigned new_val)
303{
304 __atomic_compare_exchange_4(ptr, &old_val, new_val, false,
305 __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
306 return old_val;
307}
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