source: mainline/uspace/drv/uhci-hcd/uhci_hc.c@ fbefd0e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fbefd0e was fbefd0e, checked in by Vojtech Horky <vojtechhorky@…>, 15 years ago

USB drivers less verbose on info level
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File size: 16.2 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "uhci_hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int uhci_hc_init_transfer_lists(uhci_hc_t *instance);
63static int uhci_hc_init_mem_structures(uhci_hc_t *instance);
64static void uhci_hc_init_hw(uhci_hc_t *instance);
65
66static int uhci_hc_interrupt_emulator(void *arg);
67static int uhci_hc_debug_checker(void *arg);
68
69static bool allowed_usb_packet(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
72/** Initialize UHCI hcd driver structure
73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
83 */
84int uhci_hc_init(uhci_hc_t *instance, ddf_fun_t *fun,
85 void *regs, size_t reg_size, bool interrupts)
86{
87 assert(reg_size >= sizeof(regs_t));
88 int ret;
89
90#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
91 if (ret != EOK) { \
92 usb_log_error(message); \
93 if (instance->ddf_instance) \
94 ddf_fun_destroy(instance->ddf_instance); \
95 return ret; \
96 } else (void) 0
97
98 instance->hw_interrupts = interrupts;
99 instance->hw_failures = 0;
100
101 /* Setup UHCI function. */
102 instance->ddf_instance = fun;
103
104 /* allow access to hc control registers */
105 regs_t *io;
106 ret = pio_enable(regs, reg_size, (void**)&io);
107 CHECK_RET_DEST_FUN_RETURN(ret,
108 "Failed(%d) to gain access to registers at %p: %s.\n",
109 ret, str_error(ret), io);
110 instance->registers = io;
111 usb_log_debug("Device registers at %p(%u) accessible.\n",
112 io, reg_size);
113
114 ret = uhci_hc_init_mem_structures(instance);
115 CHECK_RET_DEST_FUN_RETURN(ret,
116 "Failed to initialize UHCI memory structures.\n");
117
118 uhci_hc_init_hw(instance);
119 if (!interrupts) {
120 instance->cleaner =
121 fibril_create(uhci_hc_interrupt_emulator, instance);
122 fibril_add_ready(instance->cleaner);
123 } else {
124 /* TODO: enable interrupts here */
125 }
126
127 instance->debug_checker = fibril_create(uhci_hc_debug_checker, instance);
128 fibril_add_ready(instance->debug_checker);
129
130 return EOK;
131#undef CHECK_RET_DEST_FUN_RETURN
132}
133/*----------------------------------------------------------------------------*/
134/** Initialize UHCI hc hw resources.
135 *
136 * @param[in] instance UHCI structure to use.
137 * For magic values see UHCI Design Guide
138 */
139void uhci_hc_init_hw(uhci_hc_t *instance)
140{
141 assert(instance);
142 regs_t *registers = instance->registers;
143
144 /* Reset everything, who knows what touched it before us */
145 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
146 async_usleep(10000); /* 10ms according to USB spec */
147 pio_write_16(&registers->usbcmd, 0);
148
149 /* Reset hc, all states and counters */
150 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
151 do { async_usleep(10); }
152 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
153
154 /* Set frame to exactly 1ms */
155 pio_write_8(&registers->sofmod, 64);
156
157 /* Set frame list pointer */
158 const uint32_t pa = addr_to_phys(instance->frame_list);
159 pio_write_32(&registers->flbaseadd, pa);
160
161 if (instance->hw_interrupts) {
162 /* Enable all interrupts, but resume interrupt */
163 pio_write_16(&instance->registers->usbintr,
164 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
165 }
166
167 uint16_t status = pio_read_16(&registers->usbcmd);
168 if (status != 0)
169 usb_log_warning("Previous command value: %x.\n", status);
170
171 /* Start the hc with large(64B) packet FSBR */
172 pio_write_16(&registers->usbcmd,
173 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
174}
175/*----------------------------------------------------------------------------*/
176/** Initialize UHCI hc memory structures.
177 *
178 * @param[in] instance UHCI structure to use.
179 * @return Error code
180 * @note Should be called only once on any structure.
181 *
182 * Structures:
183 * - interrupt code (I/O addressses are customized per instance)
184 * - transfer lists (queue heads need to be accessible by the hw)
185 * - frame list page (needs to be one UHCI hw accessible 4K page)
186 */
187int uhci_hc_init_mem_structures(uhci_hc_t *instance)
188{
189 assert(instance);
190#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
191 if (ret != EOK) { \
192 usb_log_error(message); \
193 if (instance->interrupt_code.cmds != NULL) \
194 free(instance->interrupt_code.cmds); \
195 return ret; \
196 } else (void) 0
197
198 /* Init interrupt code */
199 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
200 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
201 CHECK_RET_DEST_CMDS_RETURN(ret,
202 "Failed to allocate interrupt cmds space.\n");
203
204 {
205 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
206 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
207 interrupt_commands[0].addr =
208 (void*)&instance->registers->usbsts;
209 interrupt_commands[1].addr =
210 (void*)&instance->registers->usbsts;
211 instance->interrupt_code.cmdcount =
212 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
213 }
214
215 /* Init transfer lists */
216 ret = uhci_hc_init_transfer_lists(instance);
217 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
218 usb_log_debug("Initialized transfer lists.\n");
219
220 /* Init USB frame list page*/
221 instance->frame_list = get_page();
222 ret = instance ? EOK : ENOMEM;
223 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
224 usb_log_debug("Initialized frame list.\n");
225
226 /* Set all frames to point to the first queue head */
227 const uint32_t queue =
228 instance->transfers_interrupt.queue_head_pa
229 | LINK_POINTER_QUEUE_HEAD_FLAG;
230
231 unsigned i = 0;
232 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
233 instance->frame_list[i] = queue;
234 }
235
236 /* Init device keeper*/
237 usb_device_keeper_init(&instance->device_manager);
238 usb_log_debug("Initialized device manager.\n");
239
240 return EOK;
241#undef CHECK_RET_DEST_CMDS_RETURN
242}
243/*----------------------------------------------------------------------------*/
244/** Initialize UHCI hc transfer lists.
245 *
246 * @param[in] instance UHCI structure to use.
247 * @return Error code
248 * @note Should be called only once on any structure.
249 *
250 * Initializes transfer lists and sets them in one chain to support proper
251 * USB scheduling. Sets pointer table for quick access.
252 */
253int uhci_hc_init_transfer_lists(uhci_hc_t *instance)
254{
255 assert(instance);
256#define CHECK_RET_CLEAR_RETURN(ret, message...) \
257 if (ret != EOK) { \
258 usb_log_error(message); \
259 transfer_list_fini(&instance->transfers_bulk_full); \
260 transfer_list_fini(&instance->transfers_control_full); \
261 transfer_list_fini(&instance->transfers_control_slow); \
262 transfer_list_fini(&instance->transfers_interrupt); \
263 return ret; \
264 } else (void) 0
265
266 /* initialize TODO: check errors */
267 int ret;
268 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
269 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
270
271 ret = transfer_list_init(
272 &instance->transfers_control_full, "CONTROL_FULL");
273 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
274
275 ret = transfer_list_init(
276 &instance->transfers_control_slow, "CONTROL_SLOW");
277 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
278
279 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
280 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
281
282 transfer_list_set_next(&instance->transfers_control_full,
283 &instance->transfers_bulk_full);
284 transfer_list_set_next(&instance->transfers_control_slow,
285 &instance->transfers_control_full);
286 transfer_list_set_next(&instance->transfers_interrupt,
287 &instance->transfers_control_slow);
288
289 /*FSBR*/
290#ifdef FSBR
291 transfer_list_set_next(&instance->transfers_bulk_full,
292 &instance->transfers_control_full);
293#endif
294
295 /* Assign pointers to be used during scheduling */
296 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
297 &instance->transfers_interrupt;
298 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
299 &instance->transfers_interrupt;
300 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
301 &instance->transfers_control_full;
302 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
303 &instance->transfers_control_slow;
304 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
305 &instance->transfers_bulk_full;
306
307 return EOK;
308#undef CHECK_RET_CLEAR_RETURN
309}
310/*----------------------------------------------------------------------------*/
311/** Schedule batch for execution.
312 *
313 * @param[in] instance UHCI structure to use.
314 * @param[in] batch Transfer batch to schedule.
315 * @return Error code
316 *
317 * Checks for bandwidth availability and appends the batch to the proper queue.
318 */
319int uhci_hc_schedule(uhci_hc_t *instance, usb_transfer_batch_t *batch)
320{
321 assert(instance);
322 assert(batch);
323 const int low_speed = (batch->speed == USB_SPEED_LOW);
324 if (!allowed_usb_packet(
325 low_speed, batch->transfer_type, batch->max_packet_size)) {
326 usb_log_warning(
327 "Invalid USB packet specified %s SPEED %d %zu.\n",
328 low_speed ? "LOW" : "FULL" , batch->transfer_type,
329 batch->max_packet_size);
330 return ENOTSUP;
331 }
332 /* TODO: check available bandwidth here */
333
334 transfer_list_t *list =
335 instance->transfers[batch->speed][batch->transfer_type];
336 assert(list);
337 transfer_list_add_batch(list, batch);
338
339 return EOK;
340}
341/*----------------------------------------------------------------------------*/
342/** Take action based on the interrupt cause.
343 *
344 * @param[in] instance UHCI structure to use.
345 * @param[in] status Value of the status register at the time of interrupt.
346 *
347 * Interrupt might indicate:
348 * - transaction completed, either by triggering IOC, SPD, or an error
349 * - some kind of device error
350 * - resume from suspend state (not implemented)
351 */
352void uhci_hc_interrupt(uhci_hc_t *instance, uint16_t status)
353{
354 assert(instance);
355 /* TODO: Resume interrupts are not supported */
356 /* Lower 2 bits are transaction error and transaction complete */
357 if (status & 0x3) {
358 transfer_list_remove_finished(&instance->transfers_interrupt);
359 transfer_list_remove_finished(&instance->transfers_control_slow);
360 transfer_list_remove_finished(&instance->transfers_control_full);
361 transfer_list_remove_finished(&instance->transfers_bulk_full);
362 }
363 /* bits 4 and 5 indicate hc error */
364 if (status & 0x18) {
365 usb_log_error("UHCI hardware failure!.\n");
366 ++instance->hw_failures;
367 transfer_list_abort_all(&instance->transfers_interrupt);
368 transfer_list_abort_all(&instance->transfers_control_slow);
369 transfer_list_abort_all(&instance->transfers_control_full);
370 transfer_list_abort_all(&instance->transfers_bulk_full);
371
372 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
373 /* reinitialize hw, this triggers virtual disconnect*/
374 uhci_hc_init_hw(instance);
375 } else {
376 usb_log_fatal("Too many UHCI hardware failures!.\n");
377 uhci_hc_fini(instance);
378 }
379 }
380}
381/*----------------------------------------------------------------------------*/
382/** Polling function, emulates interrupts.
383 *
384 * @param[in] arg UHCI hc structure to use.
385 * @return EOK (should never return)
386 */
387int uhci_hc_interrupt_emulator(void* arg)
388{
389 usb_log_debug("Started interrupt emulator.\n");
390 uhci_hc_t *instance = (uhci_hc_t*)arg;
391 assert(instance);
392
393 while (1) {
394 /* read and ack interrupts */
395 uint16_t status = pio_read_16(&instance->registers->usbsts);
396 pio_write_16(&instance->registers->usbsts, 0x1f);
397 if (status != 0)
398 usb_log_debug2("UHCI status: %x.\n", status);
399 uhci_hc_interrupt(instance, status);
400 async_usleep(UHCI_CLEANER_TIMEOUT);
401 }
402 return EOK;
403}
404/*---------------------------------------------------------------------------*/
405/** Debug function, checks consistency of memory structures.
406 *
407 * @param[in] arg UHCI structure to use.
408 * @return EOK (should never return)
409 */
410int uhci_hc_debug_checker(void *arg)
411{
412 uhci_hc_t *instance = (uhci_hc_t*)arg;
413 assert(instance);
414
415#define QH(queue) \
416 instance->transfers_##queue.queue_head
417
418 while (1) {
419 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
420 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
421 const uint16_t intr =
422 pio_read_16(&instance->registers->usbintr);
423
424 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
425 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
426 cmd, sts, intr);
427 }
428
429 uintptr_t frame_list =
430 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
431 if (frame_list != addr_to_phys(instance->frame_list)) {
432 usb_log_debug("Framelist address: %p vs. %p.\n",
433 frame_list, addr_to_phys(instance->frame_list));
434 }
435
436 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
437
438 uintptr_t expected_pa = instance->frame_list[frnum]
439 & LINK_POINTER_ADDRESS_MASK;
440 uintptr_t real_pa = addr_to_phys(QH(interrupt));
441 if (expected_pa != real_pa) {
442 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
443 expected_pa, frnum, real_pa);
444 }
445
446 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
447 real_pa = addr_to_phys(QH(control_slow));
448 if (expected_pa != real_pa) {
449 usb_log_debug("Control Slow QH: %p vs. %p.\n",
450 expected_pa, real_pa);
451 }
452
453 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
454 real_pa = addr_to_phys(QH(control_full));
455 if (expected_pa != real_pa) {
456 usb_log_debug("Control Full QH: %p vs. %p.\n",
457 expected_pa, real_pa);
458 }
459
460 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
461 real_pa = addr_to_phys(QH(bulk_full));
462 if (expected_pa != real_pa ) {
463 usb_log_debug("Bulk QH: %p vs. %p.\n",
464 expected_pa, real_pa);
465 }
466 async_usleep(UHCI_DEBUGER_TIMEOUT);
467 }
468 return EOK;
469#undef QH
470}
471/*----------------------------------------------------------------------------*/
472/** Check transfer packets, for USB validity
473 *
474 * @param[in] low_speed Transfer speed.
475 * @param[in] transfer Transer type
476 * @param[in] size Maximum size of used packets
477 * @return True if transaction is allowed by USB specs, false otherwise
478 */
479bool allowed_usb_packet(
480 bool low_speed, usb_transfer_type_t transfer, size_t size)
481{
482 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
483 switch(transfer)
484 {
485 case USB_TRANSFER_ISOCHRONOUS:
486 return (!low_speed && size < 1024);
487 case USB_TRANSFER_INTERRUPT:
488 return size <= (low_speed ? 8 : 64);
489 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
490 return (size <= (low_speed ? 8 : 64));
491 case USB_TRANSFER_BULK: /* device specifies its own max size */
492 return (!low_speed && size <= 64);
493 }
494 return false;
495}
496/**
497 * @}
498 */
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