source: mainline/uspace/drv/uhci-hcd/uhci_hc.c@ 2bf8f8c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2bf8f8c was fcc525d, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Limit the number of hw retries
  • Property mode set to 100644
File size: 16.1 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "uhci_hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int uhci_hc_init_transfer_lists(uhci_hc_t *instance);
63static int uhci_hc_init_mem_structures(uhci_hc_t *instance);
64static void uhci_hc_init_hw(uhci_hc_t *instance);
65
66static int uhci_hc_interrupt_emulator(void *arg);
67static int uhci_hc_debug_checker(void *arg);
68
69static bool allowed_usb_packet(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
72/** Initialize UHCI hcd driver structure
73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
83 */
84int uhci_hc_init(uhci_hc_t *instance, ddf_fun_t *fun,
85 void *regs, size_t reg_size, bool interrupts)
86{
87 assert(reg_size >= sizeof(regs_t));
88 int ret;
89
90#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
91 if (ret != EOK) { \
92 usb_log_error(message); \
93 if (instance->ddf_instance) \
94 ddf_fun_destroy(instance->ddf_instance); \
95 return ret; \
96 } else (void) 0
97
98 instance->hw_interrupts = interrupts;
99 instance->hw_failures = 0;
100
101 /* Setup UHCI function. */
102 instance->ddf_instance = fun;
103
104 /* allow access to hc control registers */
105 regs_t *io;
106 ret = pio_enable(regs, reg_size, (void**)&io);
107 CHECK_RET_DEST_FUN_RETURN(ret,
108 "Failed(%d) to gain access to registers at %p: %s.\n",
109 ret, str_error(ret), io);
110 instance->registers = io;
111 usb_log_debug("Device registers at %p(%u) accessible.\n",
112 io, reg_size);
113
114 ret = uhci_hc_init_mem_structures(instance);
115 CHECK_RET_DEST_FUN_RETURN(ret,
116 "Failed to initialize UHCI memory structures.\n");
117
118 uhci_hc_init_hw(instance);
119 if (!interrupts) {
120 instance->cleaner =
121 fibril_create(uhci_hc_interrupt_emulator, instance);
122 fibril_add_ready(instance->cleaner);
123 }
124
125 instance->debug_checker = fibril_create(uhci_hc_debug_checker, instance);
126 fibril_add_ready(instance->debug_checker);
127
128 usb_log_info("Started UHCI driver.\n");
129 return EOK;
130#undef CHECK_RET_DEST_FUN_RETURN
131}
132/*----------------------------------------------------------------------------*/
133/** Initialize UHCI hc hw resources.
134 *
135 * @param[in] instance UHCI structure to use.
136 * For magic values see UHCI Design Guide
137 */
138void uhci_hc_init_hw(uhci_hc_t *instance)
139{
140 assert(instance);
141 regs_t *registers = instance->registers;
142
143 /* Reset everything, who knows what touched it before us */
144 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
145 async_usleep(10000); /* 10ms according to USB spec */
146 pio_write_16(&registers->usbcmd, 0);
147
148 /* Reset hc, all states and counters */
149 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
150 do { async_usleep(10); }
151 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
152
153 /* Set frame to exactly 1ms */
154 pio_write_8(&registers->sofmod, 64);
155
156 /* Set frame list pointer */
157 const uint32_t pa = addr_to_phys(instance->frame_list);
158 pio_write_32(&registers->flbaseadd, pa);
159
160 if (instance->hw_interrupts) {
161 /* Enable all interrupts, but resume interrupt */
162 pio_write_16(&instance->registers->usbintr,
163 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
164 }
165
166 uint16_t status = pio_read_16(&registers->usbcmd);
167 if (status != 0)
168 usb_log_warning("Previous command value: %x.\n", status);
169
170 /* Start the hc with large(64B) packet FSBR */
171 pio_write_16(&registers->usbcmd,
172 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
173}
174/*----------------------------------------------------------------------------*/
175/** Initialize UHCI hc memory structures.
176 *
177 * @param[in] instance UHCI structure to use.
178 * @return Error code
179 * @note Should be called only once on any structure.
180 *
181 * Structures:
182 * - interrupt code (I/O addressses are customized per instance)
183 * - transfer lists (queue heads need to be accessible by the hw)
184 * - frame list page (needs to be one UHCI hw accessible 4K page)
185 */
186int uhci_hc_init_mem_structures(uhci_hc_t *instance)
187{
188 assert(instance);
189#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
190 if (ret != EOK) { \
191 usb_log_error(message); \
192 if (instance->interrupt_code.cmds != NULL) \
193 free(instance->interrupt_code.cmds); \
194 return ret; \
195 } else (void) 0
196
197 /* Init interrupt code */
198 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
199 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
200 CHECK_RET_DEST_CMDS_RETURN(ret,
201 "Failed to allocate interrupt cmds space.\n");
202
203 {
204 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
205 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
206 interrupt_commands[0].addr =
207 (void*)&instance->registers->usbsts;
208 interrupt_commands[1].addr =
209 (void*)&instance->registers->usbsts;
210 instance->interrupt_code.cmdcount =
211 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
212 }
213
214 /* Init transfer lists */
215 ret = uhci_hc_init_transfer_lists(instance);
216 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
217 usb_log_debug("Initialized transfer lists.\n");
218
219 /* Init USB frame list page*/
220 instance->frame_list = get_page();
221 ret = instance ? EOK : ENOMEM;
222 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
223 usb_log_debug("Initialized frame list.\n");
224
225 /* Set all frames to point to the first queue head */
226 const uint32_t queue =
227 instance->transfers_interrupt.queue_head_pa
228 | LINK_POINTER_QUEUE_HEAD_FLAG;
229
230 unsigned i = 0;
231 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
232 instance->frame_list[i] = queue;
233 }
234
235 /* Init device keeper*/
236 device_keeper_init(&instance->device_manager);
237 usb_log_debug("Initialized device manager.\n");
238
239 return EOK;
240#undef CHECK_RET_DEST_CMDS_RETURN
241}
242/*----------------------------------------------------------------------------*/
243/** Initialize UHCI hc transfer lists.
244 *
245 * @param[in] instance UHCI structure to use.
246 * @return Error code
247 * @note Should be called only once on any structure.
248 *
249 * Initializes transfer lists and sets them in one chain to support proper
250 * USB scheduling. Sets pointer table for quick access.
251 */
252int uhci_hc_init_transfer_lists(uhci_hc_t *instance)
253{
254 assert(instance);
255#define CHECK_RET_CLEAR_RETURN(ret, message...) \
256 if (ret != EOK) { \
257 usb_log_error(message); \
258 transfer_list_fini(&instance->transfers_bulk_full); \
259 transfer_list_fini(&instance->transfers_control_full); \
260 transfer_list_fini(&instance->transfers_control_slow); \
261 transfer_list_fini(&instance->transfers_interrupt); \
262 return ret; \
263 } else (void) 0
264
265 /* initialize TODO: check errors */
266 int ret;
267 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
268 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
269
270 ret = transfer_list_init(
271 &instance->transfers_control_full, "CONTROL_FULL");
272 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
273
274 ret = transfer_list_init(
275 &instance->transfers_control_slow, "CONTROL_SLOW");
276 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
277
278 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
279 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
280
281 transfer_list_set_next(&instance->transfers_control_full,
282 &instance->transfers_bulk_full);
283 transfer_list_set_next(&instance->transfers_control_slow,
284 &instance->transfers_control_full);
285 transfer_list_set_next(&instance->transfers_interrupt,
286 &instance->transfers_control_slow);
287
288 /*FSBR*/
289#ifdef FSBR
290 transfer_list_set_next(&instance->transfers_bulk_full,
291 &instance->transfers_control_full);
292#endif
293
294 /* Assign pointers to be used during scheduling */
295 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
296 &instance->transfers_interrupt;
297 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
298 &instance->transfers_interrupt;
299 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
300 &instance->transfers_control_full;
301 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
302 &instance->transfers_control_slow;
303 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
304 &instance->transfers_bulk_full;
305
306 return EOK;
307#undef CHECK_RET_CLEAR_RETURN
308}
309/*----------------------------------------------------------------------------*/
310/** Schedule batch for execution.
311 *
312 * @param[in] instance UHCI structure to use.
313 * @param[in] batch Transfer batch to schedule.
314 * @return Error code
315 *
316 * Checks for bandwidth availability and appends the batch to the proper queue.
317 */
318int uhci_hc_schedule(uhci_hc_t *instance, batch_t *batch)
319{
320 assert(instance);
321 assert(batch);
322 const int low_speed = (batch->speed == USB_SPEED_LOW);
323 if (!allowed_usb_packet(
324 low_speed, batch->transfer_type, batch->max_packet_size)) {
325 usb_log_warning(
326 "Invalid USB packet specified %s SPEED %d %zu.\n",
327 low_speed ? "LOW" : "FULL" , batch->transfer_type,
328 batch->max_packet_size);
329 return ENOTSUP;
330 }
331 /* TODO: check available bandwidth here */
332
333 transfer_list_t *list =
334 instance->transfers[batch->speed][batch->transfer_type];
335 assert(list);
336 transfer_list_add_batch(list, batch);
337
338 return EOK;
339}
340/*----------------------------------------------------------------------------*/
341/** Take action based on the interrupt cause.
342 *
343 * @param[in] instance UHCI structure to use.
344 * @param[in] status Value of the status register at the time of interrupt.
345 *
346 * Interrupt might indicate:
347 * - transaction completed, either by triggering IOC, SPD, or an error
348 * - some kind of device error
349 * - resume from suspend state (not implemented)
350 */
351void uhci_hc_interrupt(uhci_hc_t *instance, uint16_t status)
352{
353 assert(instance);
354 /* TODO: Resume interrupts are not supported */
355 /* Lower 2 bits are transaction error and transaction complete */
356 if (status & 0x3) {
357 transfer_list_remove_finished(&instance->transfers_interrupt);
358 transfer_list_remove_finished(&instance->transfers_control_slow);
359 transfer_list_remove_finished(&instance->transfers_control_full);
360 transfer_list_remove_finished(&instance->transfers_bulk_full);
361 }
362 /* bits 4 and 5 indicate hc error */
363 if (status & 0x18) {
364 usb_log_error("UHCI hardware failure!.\n");
365 ++instance->hw_failures;
366 transfer_list_abort_all(&instance->transfers_interrupt);
367 transfer_list_abort_all(&instance->transfers_control_slow);
368 transfer_list_abort_all(&instance->transfers_control_full);
369 transfer_list_abort_all(&instance->transfers_bulk_full);
370
371 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
372 /* reinitialize hw, this triggers virtual disconnect*/
373 uhci_hc_init_hw(instance);
374 } else {
375 usb_log_fatal("Too many UHCI hardware failures!.\n");
376 uhci_hc_fini(instance);
377 }
378 }
379}
380/*----------------------------------------------------------------------------*/
381/** Polling function, emulates interrupts.
382 *
383 * @param[in] arg UHCI hc structure to use.
384 * @return EOK (should never return)
385 */
386int uhci_hc_interrupt_emulator(void* arg)
387{
388 usb_log_debug("Started interrupt emulator.\n");
389 uhci_hc_t *instance = (uhci_hc_t*)arg;
390 assert(instance);
391
392 while (1) {
393 /* read and ack interrupts */
394 uint16_t status = pio_read_16(&instance->registers->usbsts);
395 pio_write_16(&instance->registers->usbsts, 0x1f);
396 if (status != 0)
397 usb_log_debug2("UHCI status: %x.\n", status);
398 uhci_hc_interrupt(instance, status);
399 async_usleep(UHCI_CLEANER_TIMEOUT);
400 }
401 return EOK;
402}
403/*---------------------------------------------------------------------------*/
404/** Debug function, checks consistency of memory structures.
405 *
406 * @param[in] arg UHCI structure to use.
407 * @return EOK (should never return)
408 */
409int uhci_hc_debug_checker(void *arg)
410{
411 uhci_hc_t *instance = (uhci_hc_t*)arg;
412 assert(instance);
413
414#define QH(queue) \
415 instance->transfers_##queue.queue_head
416
417 while (1) {
418 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
419 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
420 const uint16_t intr =
421 pio_read_16(&instance->registers->usbintr);
422
423 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
424 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
425 cmd, sts, intr);
426 }
427
428 uintptr_t frame_list =
429 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
430 if (frame_list != addr_to_phys(instance->frame_list)) {
431 usb_log_debug("Framelist address: %p vs. %p.\n",
432 frame_list, addr_to_phys(instance->frame_list));
433 }
434
435 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
436
437 uintptr_t expected_pa = instance->frame_list[frnum]
438 & LINK_POINTER_ADDRESS_MASK;
439 uintptr_t real_pa = addr_to_phys(QH(interrupt));
440 if (expected_pa != real_pa) {
441 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
442 expected_pa, frnum, real_pa);
443 }
444
445 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
446 real_pa = addr_to_phys(QH(control_slow));
447 if (expected_pa != real_pa) {
448 usb_log_debug("Control Slow QH: %p vs. %p.\n",
449 expected_pa, real_pa);
450 }
451
452 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
453 real_pa = addr_to_phys(QH(control_full));
454 if (expected_pa != real_pa) {
455 usb_log_debug("Control Full QH: %p vs. %p.\n",
456 expected_pa, real_pa);
457 }
458
459 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
460 real_pa = addr_to_phys(QH(bulk_full));
461 if (expected_pa != real_pa ) {
462 usb_log_debug("Bulk QH: %p vs. %p.\n",
463 expected_pa, real_pa);
464 }
465 async_usleep(UHCI_DEBUGER_TIMEOUT);
466 }
467 return EOK;
468#undef QH
469}
470/*----------------------------------------------------------------------------*/
471/** Check transfer packets, for USB validity
472 *
473 * @param[in] low_speed Transfer speed.
474 * @param[in] transfer Transer type
475 * @param[in] size Maximum size of used packets
476 * @return True if transaction is allowed by USB specs, false otherwise
477 */
478bool allowed_usb_packet(
479 bool low_speed, usb_transfer_type_t transfer, size_t size)
480{
481 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
482 switch(transfer)
483 {
484 case USB_TRANSFER_ISOCHRONOUS:
485 return (!low_speed && size < 1024);
486 case USB_TRANSFER_INTERRUPT:
487 return size <= (low_speed ? 8 : 64);
488 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
489 return (size <= (low_speed ? 8 : 64));
490 case USB_TRANSFER_BULK: /* device specifies its own max size */
491 return (!low_speed && size <= 64);
492 }
493 return false;
494}
495/**
496 * @}
497 */
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