source: mainline/uspace/drv/uhci-hcd/uhci_hc.c@ 17ceb72

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 17ceb72 was 17ceb72, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Doxygen

  • Property mode set to 100644
File size: 15.3 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "uhci_hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int uhci_hc_init_transfer_lists(uhci_hc_t *instance);
63static int uhci_hc_init_mem_structures(uhci_hc_t *instance);
64static void uhci_hc_init_hw(uhci_hc_t *instance);
65
66static int uhci_hc_interrupt_emulator(void *arg);
67static int uhci_hc_debug_checker(void *arg);
68
69static bool allowed_usb_packet(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
72/** Initialize UHCI hcd driver structure
73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
83 */
84int uhci_hc_init(uhci_hc_t *instance, ddf_fun_t *fun, void *regs, size_t reg_size)
85{
86 assert(reg_size >= sizeof(regs_t));
87 int ret;
88
89#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
90 if (ret != EOK) { \
91 usb_log_error(message); \
92 if (instance->ddf_instance) \
93 ddf_fun_destroy(instance->ddf_instance); \
94 return ret; \
95 } else (void) 0
96
97 /* Setup UHCI function. */
98 instance->ddf_instance = fun;
99
100 /* allow access to hc control registers */
101 regs_t *io;
102 ret = pio_enable(regs, reg_size, (void**)&io);
103 CHECK_RET_DEST_FUN_RETURN(ret,
104 "Failed(%d) to gain access to registers at %p: %s.\n",
105 ret, str_error(ret), io);
106 instance->registers = io;
107 usb_log_debug("Device registers at %p(%u) accessible.\n",
108 io, reg_size);
109
110 ret = uhci_hc_init_mem_structures(instance);
111 CHECK_RET_DEST_FUN_RETURN(ret,
112 "Failed to initialize UHCI memory structures.\n");
113
114 uhci_hc_init_hw(instance);
115 instance->cleaner =
116 fibril_create(uhci_hc_interrupt_emulator, instance);
117 fibril_add_ready(instance->cleaner);
118
119 instance->debug_checker = fibril_create(uhci_hc_debug_checker, instance);
120 fibril_add_ready(instance->debug_checker);
121
122 usb_log_info("Started UHCI driver.\n");
123 return EOK;
124#undef CHECK_RET_DEST_FUN_RETURN
125}
126/*----------------------------------------------------------------------------*/
127/** Initialize UHCI hc hw resources.
128 *
129 * @param[in] instance UHCI structure to use.
130 * For magic values see UHCI Design Guide
131 */
132void uhci_hc_init_hw(uhci_hc_t *instance)
133{
134 assert(instance);
135 regs_t *registers = instance->registers;
136
137 /* Reset everything, who knows what touched it before us */
138 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
139 async_usleep(10000); /* 10ms according to USB spec */
140 pio_write_16(&registers->usbcmd, 0);
141
142 /* Reset hc, all states and counters */
143 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
144 do { async_usleep(10); }
145 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
146
147 /* Set framelist pointer */
148 const uint32_t pa = addr_to_phys(instance->frame_list);
149 pio_write_32(&registers->flbaseadd, pa);
150
151 /* Enable all interrupts, but resume interrupt */
152 pio_write_16(&instance->registers->usbintr,
153 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
154
155 uint16_t status = pio_read_16(&registers->usbcmd);
156 if (status != 0)
157 usb_log_warning("Previous command value: %x.\n", status);
158
159 /* Start the hc with large(64B) packet FSBR */
160 pio_write_16(&registers->usbcmd,
161 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
162}
163/*----------------------------------------------------------------------------*/
164/** Initialize UHCI hc memory structures.
165 *
166 * @param[in] instance UHCI structure to use.
167 * @return Error code
168 * @note Should be called only once on any structure.
169 *
170 * Structures:
171 * - interrupt code (I/O addressses are customized per instance)
172 * - transfer lists (queue heads need to be accessible by the hw)
173 * - frame list page (needs to be one UHCI hw accessible 4K page)
174 */
175int uhci_hc_init_mem_structures(uhci_hc_t *instance)
176{
177 assert(instance);
178#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
179 if (ret != EOK) { \
180 usb_log_error(message); \
181 if (instance->interrupt_code.cmds != NULL) \
182 free(instance->interrupt_code.cmds); \
183 return ret; \
184 } else (void) 0
185
186 /* Init interrupt code */
187 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
188 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
189 CHECK_RET_DEST_CMDS_RETURN(ret,
190 "Failed to allocate interrupt cmds space.\n");
191
192 {
193 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
194 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
195 interrupt_commands[0].addr =
196 (void*)&instance->registers->usbsts;
197 interrupt_commands[1].addr =
198 (void*)&instance->registers->usbsts;
199 instance->interrupt_code.cmdcount =
200 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
201 }
202
203 /* Init transfer lists */
204 ret = uhci_hc_init_transfer_lists(instance);
205 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
206 usb_log_debug("Initialized transfer lists.\n");
207
208 /* Init USB frame list page*/
209 instance->frame_list = get_page();
210 ret = instance ? EOK : ENOMEM;
211 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
212 usb_log_debug("Initialized frame list.\n");
213
214 /* Set all frames to point to the first queue head */
215 const uint32_t queue =
216 instance->transfers_interrupt.queue_head_pa
217 | LINK_POINTER_QUEUE_HEAD_FLAG;
218
219 unsigned i = 0;
220 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
221 instance->frame_list[i] = queue;
222 }
223
224 /* Init device keeper*/
225 device_keeper_init(&instance->device_manager);
226 usb_log_debug("Initialized device manager.\n");
227
228 return EOK;
229#undef CHECK_RET_DEST_CMDS_RETURN
230}
231/*----------------------------------------------------------------------------*/
232/** Initialize UHCI hc transfer lists.
233 *
234 * @param[in] instance UHCI structure to use.
235 * @return Error code
236 * @note Should be called only once on any structure.
237 *
238 * Initializes transfer lists and sets them in one chain to support proper
239 * USB scheduling. Sets pointer table for quick access.
240 */
241int uhci_hc_init_transfer_lists(uhci_hc_t *instance)
242{
243 assert(instance);
244#define CHECK_RET_CLEAR_RETURN(ret, message...) \
245 if (ret != EOK) { \
246 usb_log_error(message); \
247 transfer_list_fini(&instance->transfers_bulk_full); \
248 transfer_list_fini(&instance->transfers_control_full); \
249 transfer_list_fini(&instance->transfers_control_slow); \
250 transfer_list_fini(&instance->transfers_interrupt); \
251 return ret; \
252 } else (void) 0
253
254 /* initialize TODO: check errors */
255 int ret;
256 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
257 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
258
259 ret = transfer_list_init(
260 &instance->transfers_control_full, "CONTROL_FULL");
261 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
262
263 ret = transfer_list_init(
264 &instance->transfers_control_slow, "CONTROL_SLOW");
265 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
266
267 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
268 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
269
270 transfer_list_set_next(&instance->transfers_control_full,
271 &instance->transfers_bulk_full);
272 transfer_list_set_next(&instance->transfers_control_slow,
273 &instance->transfers_control_full);
274 transfer_list_set_next(&instance->transfers_interrupt,
275 &instance->transfers_control_slow);
276
277 /*FSBR*/
278#ifdef FSBR
279 transfer_list_set_next(&instance->transfers_bulk_full,
280 &instance->transfers_control_full);
281#endif
282
283 /* Assign pointers to be used during scheduling */
284 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
285 &instance->transfers_interrupt;
286 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
287 &instance->transfers_interrupt;
288 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
289 &instance->transfers_control_full;
290 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
291 &instance->transfers_control_slow;
292 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
293 &instance->transfers_bulk_full;
294
295 return EOK;
296#undef CHECK_RET_CLEAR_RETURN
297}
298/*----------------------------------------------------------------------------*/
299/** Schedule batch for execution.
300 *
301 * @param[in] instance UHCI structure to use.
302 * @param[in] batch Transfer batch to schedule.
303 * @return Error code
304 *
305 * Checks for bandwidth availability and appends the batch to the proper queue.
306 */
307int uhci_hc_schedule(uhci_hc_t *instance, batch_t *batch)
308{
309 assert(instance);
310 assert(batch);
311 const int low_speed = (batch->speed == USB_SPEED_LOW);
312 if (!allowed_usb_packet(
313 low_speed, batch->transfer_type, batch->max_packet_size)) {
314 usb_log_warning(
315 "Invalid USB packet specified %s SPEED %d %zu.\n",
316 low_speed ? "LOW" : "FULL" , batch->transfer_type,
317 batch->max_packet_size);
318 return ENOTSUP;
319 }
320 /* TODO: check available bandwidth here */
321
322 transfer_list_t *list =
323 instance->transfers[batch->speed][batch->transfer_type];
324 assert(list);
325 transfer_list_add_batch(list, batch);
326
327 return EOK;
328}
329/*----------------------------------------------------------------------------*/
330/** Take action based on the interrupt cause.
331 *
332 * @param[in] instance UHCI structure to use.
333 * @param[in] status Value of the status register at the time of interrupt.
334 *
335 * Interrupt might indicate:
336 * - transaction completed, either by triggering IOC, SPD, or an error
337 * - some kind of device error
338 * - resume from suspend state (not implemented)
339 */
340void uhci_hc_interrupt(uhci_hc_t *instance, uint16_t status)
341{
342 assert(instance);
343 /* TODO: Check interrupt cause here */
344 /* Lower 2 bits are transaction error and transaction complete */
345 if (status & 0x3) {
346 transfer_list_remove_finished(&instance->transfers_interrupt);
347 transfer_list_remove_finished(&instance->transfers_control_slow);
348 transfer_list_remove_finished(&instance->transfers_control_full);
349 transfer_list_remove_finished(&instance->transfers_bulk_full);
350 }
351}
352/*----------------------------------------------------------------------------*/
353/** Polling function, emulates interrupts.
354 *
355 * @param[in] arg UHCI hc structure to use.
356 * @return EOK (should never return)
357 */
358int uhci_hc_interrupt_emulator(void* arg)
359{
360 usb_log_debug("Started interrupt emulator.\n");
361 uhci_hc_t *instance = (uhci_hc_t*)arg;
362 assert(instance);
363
364 while (1) {
365 /* read and ack interrupts */
366 uint16_t status = pio_read_16(&instance->registers->usbsts);
367 pio_write_16(&instance->registers->usbsts, 0x1f);
368 if (status != 0)
369 usb_log_debug2("UHCI status: %x.\n", status);
370 uhci_hc_interrupt(instance, status);
371 async_usleep(UHCI_CLEANER_TIMEOUT);
372 }
373 return EOK;
374}
375/*---------------------------------------------------------------------------*/
376/** Debug function, checks consistency of memory structures.
377 *
378 * @param[in] arg UHCI structure to use.
379 * @return EOK (should never return)
380 */
381int uhci_hc_debug_checker(void *arg)
382{
383 uhci_hc_t *instance = (uhci_hc_t*)arg;
384 assert(instance);
385
386#define QH(queue) \
387 instance->transfers_##queue.queue_head
388
389 while (1) {
390 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
391 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
392 const uint16_t intr =
393 pio_read_16(&instance->registers->usbintr);
394
395 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
396 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
397 cmd, sts, intr);
398 }
399
400 uintptr_t frame_list =
401 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
402 if (frame_list != addr_to_phys(instance->frame_list)) {
403 usb_log_debug("Framelist address: %p vs. %p.\n",
404 frame_list, addr_to_phys(instance->frame_list));
405 }
406
407 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
408
409 uintptr_t expected_pa = instance->frame_list[frnum]
410 & LINK_POINTER_ADDRESS_MASK;
411 uintptr_t real_pa = addr_to_phys(QH(interrupt));
412 if (expected_pa != real_pa) {
413 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
414 expected_pa, frnum, real_pa);
415 }
416
417 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
418 real_pa = addr_to_phys(QH(control_slow));
419 if (expected_pa != real_pa) {
420 usb_log_debug("Control Slow QH: %p vs. %p.\n",
421 expected_pa, real_pa);
422 }
423
424 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
425 real_pa = addr_to_phys(QH(control_full));
426 if (expected_pa != real_pa) {
427 usb_log_debug("Control Full QH: %p vs. %p.\n",
428 expected_pa, real_pa);
429 }
430
431 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
432 real_pa = addr_to_phys(QH(bulk_full));
433 if (expected_pa != real_pa ) {
434 usb_log_debug("Bulk QH: %p vs. %p.\n",
435 expected_pa, real_pa);
436 }
437 async_usleep(UHCI_DEBUGER_TIMEOUT);
438 }
439 return EOK;
440#undef QH
441}
442/*----------------------------------------------------------------------------*/
443/** Check transfer packets, for USB validity
444 *
445 * @param[in] low_speed Transfer speed.
446 * @param[in] transfer Transer type
447 * @param[in] size Maximum size of used packets
448 * @return True if transaction is allowed by USB specs, false otherwise
449 */
450bool allowed_usb_packet(
451 bool low_speed, usb_transfer_type_t transfer, size_t size)
452{
453 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
454 switch(transfer)
455 {
456 case USB_TRANSFER_ISOCHRONOUS:
457 return (!low_speed && size < 1024);
458 case USB_TRANSFER_INTERRUPT:
459 return size <= (low_speed ? 8 : 64);
460 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
461 return (size <= (low_speed ? 8 : 64));
462 case USB_TRANSFER_BULK: /* device specifies its own max size */
463 return (!low_speed && size <= 64);
464 }
465 return false;
466}
467/**
468 * @}
469 */
Note: See TracBrowser for help on using the repository browser.