1 | /*
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2 | * Copyright (c) 2011 Jan Vesely
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 | /** @addtogroup drvusbuhcihc
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29 | * @{
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30 | */
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31 | /** @file
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32 | * @brief UHCI Host controller driver routines
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33 | */
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34 | #include <errno.h>
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35 | #include <str_error.h>
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36 | #include <adt/list.h>
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37 | #include <libarch/ddi.h>
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38 |
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39 | #include <usb/debug.h>
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40 | #include <usb/usb.h>
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41 | #include <usb/ddfiface.h>
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42 | #include <usb_iface.h>
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43 |
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44 | #include "uhci_hc.h"
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45 |
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46 | static irq_cmd_t uhci_cmds[] = {
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47 | {
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48 | .cmd = CMD_PIO_READ_16,
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49 | .addr = NULL, /* patched for every instance */
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50 | .dstarg = 1
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51 | },
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52 | {
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53 | .cmd = CMD_PIO_WRITE_16,
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54 | .addr = NULL, /* pathed for every instance */
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55 | .value = 0x1f
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56 | },
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57 | {
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58 | .cmd = CMD_ACCEPT
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59 | }
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60 | };
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61 | /*----------------------------------------------------------------------------*/
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62 | static int uhci_hc_init_transfer_lists(uhci_hc_t *instance);
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63 | static int uhci_hc_init_mem_structures(uhci_hc_t *instance);
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64 | static void uhci_hc_init_hw(uhci_hc_t *instance);
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65 |
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66 | static int uhci_hc_interrupt_emulator(void *arg);
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67 | static int uhci_hc_debug_checker(void *arg);
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68 |
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69 | static bool allowed_usb_packet(
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70 | bool low_speed, usb_transfer_type_t transfer, size_t size);
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71 | /*----------------------------------------------------------------------------*/
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72 | /** Initialize UHCI hcd driver structure
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73 | *
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74 | * @param[in] instance Memory place to initialize.
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75 | * @param[in] fun DDF function.
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76 | * @param[in] regs Address of I/O control registers.
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77 | * @param[in] size Size of I/O control registers.
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78 | * @return Error code.
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79 | * @note Should be called only once on any structure.
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80 | *
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81 | * Initializes memory structures, starts up hw, and launches debugger and
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82 | * interrupt fibrils.
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83 | */
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84 | int uhci_hc_init(uhci_hc_t *instance, ddf_fun_t *fun, void *regs, size_t reg_size)
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85 | {
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86 | assert(reg_size >= sizeof(regs_t));
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87 | int ret;
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88 |
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89 | #define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
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90 | if (ret != EOK) { \
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91 | usb_log_error(message); \
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92 | if (instance->ddf_instance) \
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93 | ddf_fun_destroy(instance->ddf_instance); \
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94 | return ret; \
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95 | } else (void) 0
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96 |
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97 | /* Setup UHCI function. */
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98 | instance->ddf_instance = fun;
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99 |
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100 | /* allow access to hc control registers */
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101 | regs_t *io;
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102 | ret = pio_enable(regs, reg_size, (void**)&io);
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103 | CHECK_RET_DEST_FUN_RETURN(ret,
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104 | "Failed(%d) to gain access to registers at %p: %s.\n",
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105 | ret, str_error(ret), io);
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106 | instance->registers = io;
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107 | usb_log_debug("Device registers at %p(%u) accessible.\n",
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108 | io, reg_size);
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109 |
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110 | ret = uhci_hc_init_mem_structures(instance);
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111 | CHECK_RET_DEST_FUN_RETURN(ret,
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112 | "Failed to initialize UHCI memory structures.\n");
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113 |
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114 | uhci_hc_init_hw(instance);
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115 | instance->cleaner =
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116 | fibril_create(uhci_hc_interrupt_emulator, instance);
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117 | fibril_add_ready(instance->cleaner);
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118 |
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119 | instance->debug_checker = fibril_create(uhci_hc_debug_checker, instance);
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120 | fibril_add_ready(instance->debug_checker);
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121 |
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122 | usb_log_info("Started UHCI driver.\n");
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123 | return EOK;
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124 | #undef CHECK_RET_DEST_FUN_RETURN
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125 | }
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126 | /*----------------------------------------------------------------------------*/
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127 | /** Initialize UHCI hc hw resources.
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128 | *
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129 | * @param[in] instance UHCI structure to use.
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130 | * For magic values see UHCI Design Guide
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131 | */
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132 | void uhci_hc_init_hw(uhci_hc_t *instance)
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133 | {
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134 | assert(instance);
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135 | regs_t *registers = instance->registers;
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136 |
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137 | /* Reset everything, who knows what touched it before us */
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138 | pio_write_16(®isters->usbcmd, UHCI_CMD_GLOBAL_RESET);
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139 | async_usleep(10000); /* 10ms according to USB spec */
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140 | pio_write_16(®isters->usbcmd, 0);
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141 |
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142 | /* Reset hc, all states and counters */
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143 | pio_write_16(®isters->usbcmd, UHCI_CMD_HCRESET);
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144 | do { async_usleep(10); }
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145 | while ((pio_read_16(®isters->usbcmd) & UHCI_CMD_HCRESET) != 0);
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146 |
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147 | /* Set framelist pointer */
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148 | const uint32_t pa = addr_to_phys(instance->frame_list);
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149 | pio_write_32(®isters->flbaseadd, pa);
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150 |
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151 | /* Enable all interrupts, but resume interrupt */
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152 | pio_write_16(&instance->registers->usbintr,
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153 | UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
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154 |
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155 | uint16_t status = pio_read_16(®isters->usbcmd);
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156 | if (status != 0)
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157 | usb_log_warning("Previous command value: %x.\n", status);
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158 |
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159 | /* Start the hc with large(64B) packet FSBR */
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160 | pio_write_16(®isters->usbcmd,
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161 | UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
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162 | }
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163 | /*----------------------------------------------------------------------------*/
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164 | /** Initialize UHCI hc memory structures.
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165 | *
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166 | * @param[in] instance UHCI structure to use.
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167 | * @return Error code
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168 | * @note Should be called only once on any structure.
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169 | *
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170 | * Structures:
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171 | * - interrupt code (I/O addressses are customized per instance)
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172 | * - transfer lists (queue heads need to be accessible by the hw)
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173 | * - frame list page (needs to be one UHCI hw accessible 4K page)
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174 | */
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175 | int uhci_hc_init_mem_structures(uhci_hc_t *instance)
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176 | {
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177 | assert(instance);
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178 | #define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
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179 | if (ret != EOK) { \
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180 | usb_log_error(message); \
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181 | if (instance->interrupt_code.cmds != NULL) \
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182 | free(instance->interrupt_code.cmds); \
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183 | return ret; \
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184 | } else (void) 0
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185 |
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186 | /* Init interrupt code */
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187 | instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
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188 | int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
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189 | CHECK_RET_DEST_CMDS_RETURN(ret,
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190 | "Failed to allocate interrupt cmds space.\n");
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191 |
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192 | {
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193 | irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
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194 | memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
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195 | interrupt_commands[0].addr =
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196 | (void*)&instance->registers->usbsts;
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197 | interrupt_commands[1].addr =
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198 | (void*)&instance->registers->usbsts;
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199 | instance->interrupt_code.cmdcount =
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200 | sizeof(uhci_cmds) / sizeof(irq_cmd_t);
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201 | }
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202 |
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203 | /* Init transfer lists */
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204 | ret = uhci_hc_init_transfer_lists(instance);
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205 | CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
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206 | usb_log_debug("Initialized transfer lists.\n");
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207 |
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208 | /* Init USB frame list page*/
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209 | instance->frame_list = get_page();
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210 | ret = instance ? EOK : ENOMEM;
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211 | CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
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212 | usb_log_debug("Initialized frame list.\n");
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213 |
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214 | /* Set all frames to point to the first queue head */
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215 | const uint32_t queue =
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216 | instance->transfers_interrupt.queue_head_pa
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217 | | LINK_POINTER_QUEUE_HEAD_FLAG;
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218 |
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219 | unsigned i = 0;
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220 | for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
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221 | instance->frame_list[i] = queue;
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222 | }
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223 |
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224 | /* Init device keeper*/
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225 | device_keeper_init(&instance->device_manager);
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226 | usb_log_debug("Initialized device manager.\n");
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227 |
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228 | return EOK;
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229 | #undef CHECK_RET_DEST_CMDS_RETURN
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230 | }
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231 | /*----------------------------------------------------------------------------*/
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232 | /** Initialize UHCI hc transfer lists.
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233 | *
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234 | * @param[in] instance UHCI structure to use.
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235 | * @return Error code
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236 | * @note Should be called only once on any structure.
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237 | *
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238 | * Initializes transfer lists and sets them in one chain to support proper
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239 | * USB scheduling. Sets pointer table for quick access.
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240 | */
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241 | int uhci_hc_init_transfer_lists(uhci_hc_t *instance)
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242 | {
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243 | assert(instance);
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244 | #define CHECK_RET_CLEAR_RETURN(ret, message...) \
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245 | if (ret != EOK) { \
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246 | usb_log_error(message); \
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247 | transfer_list_fini(&instance->transfers_bulk_full); \
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248 | transfer_list_fini(&instance->transfers_control_full); \
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249 | transfer_list_fini(&instance->transfers_control_slow); \
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250 | transfer_list_fini(&instance->transfers_interrupt); \
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251 | return ret; \
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252 | } else (void) 0
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253 |
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254 | /* initialize TODO: check errors */
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255 | int ret;
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256 | ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
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257 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
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258 |
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259 | ret = transfer_list_init(
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260 | &instance->transfers_control_full, "CONTROL_FULL");
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261 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
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262 |
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263 | ret = transfer_list_init(
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264 | &instance->transfers_control_slow, "CONTROL_SLOW");
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265 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
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266 |
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267 | ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
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268 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
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269 |
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270 | transfer_list_set_next(&instance->transfers_control_full,
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271 | &instance->transfers_bulk_full);
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272 | transfer_list_set_next(&instance->transfers_control_slow,
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273 | &instance->transfers_control_full);
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274 | transfer_list_set_next(&instance->transfers_interrupt,
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275 | &instance->transfers_control_slow);
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276 |
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277 | /*FSBR*/
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278 | #ifdef FSBR
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279 | transfer_list_set_next(&instance->transfers_bulk_full,
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280 | &instance->transfers_control_full);
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281 | #endif
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282 |
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283 | /* Assign pointers to be used during scheduling */
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284 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
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285 | &instance->transfers_interrupt;
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286 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
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287 | &instance->transfers_interrupt;
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288 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
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289 | &instance->transfers_control_full;
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290 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
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291 | &instance->transfers_control_slow;
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292 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
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293 | &instance->transfers_bulk_full;
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294 |
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295 | return EOK;
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296 | #undef CHECK_RET_CLEAR_RETURN
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297 | }
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298 | /*----------------------------------------------------------------------------*/
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299 | /** Schedule batch for execution.
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300 | *
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301 | * @param[in] instance UHCI structure to use.
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302 | * @param[in] batch Transfer batch to schedule.
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303 | * @return Error code
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304 | *
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305 | * Checks for bandwidth availability and appends the batch to the proper queue.
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306 | */
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307 | int uhci_hc_schedule(uhci_hc_t *instance, batch_t *batch)
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308 | {
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309 | assert(instance);
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310 | assert(batch);
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311 | const int low_speed = (batch->speed == USB_SPEED_LOW);
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312 | if (!allowed_usb_packet(
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313 | low_speed, batch->transfer_type, batch->max_packet_size)) {
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314 | usb_log_warning(
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315 | "Invalid USB packet specified %s SPEED %d %zu.\n",
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316 | low_speed ? "LOW" : "FULL" , batch->transfer_type,
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317 | batch->max_packet_size);
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318 | return ENOTSUP;
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319 | }
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320 | /* TODO: check available bandwidth here */
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321 |
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322 | transfer_list_t *list =
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323 | instance->transfers[batch->speed][batch->transfer_type];
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324 | assert(list);
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325 | transfer_list_add_batch(list, batch);
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326 |
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327 | return EOK;
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328 | }
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329 | /*----------------------------------------------------------------------------*/
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330 | /** Take action based on the interrupt cause.
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331 | *
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332 | * @param[in] instance UHCI structure to use.
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333 | * @param[in] status Value of the status register at the time of interrupt.
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334 | *
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335 | * Interrupt might indicate:
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336 | * - transaction completed, either by triggering IOC, SPD, or an error
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337 | * - some kind of device error
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338 | * - resume from suspend state (not implemented)
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339 | */
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340 | void uhci_hc_interrupt(uhci_hc_t *instance, uint16_t status)
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341 | {
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342 | assert(instance);
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343 | /* TODO: Check interrupt cause here */
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344 | /* Lower 2 bits are transaction error and transaction complete */
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345 | if (status & 0x3) {
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346 | transfer_list_remove_finished(&instance->transfers_interrupt);
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347 | transfer_list_remove_finished(&instance->transfers_control_slow);
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348 | transfer_list_remove_finished(&instance->transfers_control_full);
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349 | transfer_list_remove_finished(&instance->transfers_bulk_full);
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350 | }
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351 | }
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352 | /*----------------------------------------------------------------------------*/
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353 | /** Polling function, emulates interrupts.
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354 | *
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355 | * @param[in] arg UHCI hc structure to use.
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356 | * @return EOK (should never return)
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357 | */
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358 | int uhci_hc_interrupt_emulator(void* arg)
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359 | {
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360 | usb_log_debug("Started interrupt emulator.\n");
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361 | uhci_hc_t *instance = (uhci_hc_t*)arg;
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362 | assert(instance);
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363 |
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364 | while (1) {
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365 | /* read and ack interrupts */
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366 | uint16_t status = pio_read_16(&instance->registers->usbsts);
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367 | pio_write_16(&instance->registers->usbsts, 0x1f);
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368 | if (status != 0)
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369 | usb_log_debug2("UHCI status: %x.\n", status);
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370 | uhci_hc_interrupt(instance, status);
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371 | async_usleep(UHCI_CLEANER_TIMEOUT);
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372 | }
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373 | return EOK;
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374 | }
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375 | /*---------------------------------------------------------------------------*/
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376 | /** Debug function, checks consistency of memory structures.
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377 | *
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378 | * @param[in] arg UHCI structure to use.
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379 | * @return EOK (should never return)
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380 | */
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381 | int uhci_hc_debug_checker(void *arg)
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382 | {
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383 | uhci_hc_t *instance = (uhci_hc_t*)arg;
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384 | assert(instance);
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385 |
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386 | #define QH(queue) \
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387 | instance->transfers_##queue.queue_head
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388 |
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389 | while (1) {
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390 | const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
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391 | const uint16_t sts = pio_read_16(&instance->registers->usbsts);
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392 | const uint16_t intr =
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393 | pio_read_16(&instance->registers->usbintr);
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394 |
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395 | if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
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396 | usb_log_debug2("Command: %X Status: %X Intr: %x\n",
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397 | cmd, sts, intr);
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398 | }
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399 |
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400 | uintptr_t frame_list =
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401 | pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
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402 | if (frame_list != addr_to_phys(instance->frame_list)) {
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403 | usb_log_debug("Framelist address: %p vs. %p.\n",
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404 | frame_list, addr_to_phys(instance->frame_list));
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405 | }
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406 |
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407 | int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
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408 |
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409 | uintptr_t expected_pa = instance->frame_list[frnum]
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410 | & LINK_POINTER_ADDRESS_MASK;
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411 | uintptr_t real_pa = addr_to_phys(QH(interrupt));
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412 | if (expected_pa != real_pa) {
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413 | usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
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414 | expected_pa, frnum, real_pa);
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415 | }
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416 |
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417 | expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
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418 | real_pa = addr_to_phys(QH(control_slow));
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419 | if (expected_pa != real_pa) {
|
---|
420 | usb_log_debug("Control Slow QH: %p vs. %p.\n",
|
---|
421 | expected_pa, real_pa);
|
---|
422 | }
|
---|
423 |
|
---|
424 | expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
425 | real_pa = addr_to_phys(QH(control_full));
|
---|
426 | if (expected_pa != real_pa) {
|
---|
427 | usb_log_debug("Control Full QH: %p vs. %p.\n",
|
---|
428 | expected_pa, real_pa);
|
---|
429 | }
|
---|
430 |
|
---|
431 | expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
432 | real_pa = addr_to_phys(QH(bulk_full));
|
---|
433 | if (expected_pa != real_pa ) {
|
---|
434 | usb_log_debug("Bulk QH: %p vs. %p.\n",
|
---|
435 | expected_pa, real_pa);
|
---|
436 | }
|
---|
437 | async_usleep(UHCI_DEBUGER_TIMEOUT);
|
---|
438 | }
|
---|
439 | return EOK;
|
---|
440 | #undef QH
|
---|
441 | }
|
---|
442 | /*----------------------------------------------------------------------------*/
|
---|
443 | /** Check transfer packets, for USB validity
|
---|
444 | *
|
---|
445 | * @param[in] low_speed Transfer speed.
|
---|
446 | * @param[in] transfer Transer type
|
---|
447 | * @param[in] size Maximum size of used packets
|
---|
448 | * @return True if transaction is allowed by USB specs, false otherwise
|
---|
449 | */
|
---|
450 | bool allowed_usb_packet(
|
---|
451 | bool low_speed, usb_transfer_type_t transfer, size_t size)
|
---|
452 | {
|
---|
453 | /* see USB specification chapter 5.5-5.8 for magic numbers used here */
|
---|
454 | switch(transfer)
|
---|
455 | {
|
---|
456 | case USB_TRANSFER_ISOCHRONOUS:
|
---|
457 | return (!low_speed && size < 1024);
|
---|
458 | case USB_TRANSFER_INTERRUPT:
|
---|
459 | return size <= (low_speed ? 8 : 64);
|
---|
460 | case USB_TRANSFER_CONTROL: /* device specifies its own max size */
|
---|
461 | return (size <= (low_speed ? 8 : 64));
|
---|
462 | case USB_TRANSFER_BULK: /* device specifies its own max size */
|
---|
463 | return (!low_speed && size <= 64);
|
---|
464 | }
|
---|
465 | return false;
|
---|
466 | }
|
---|
467 | /**
|
---|
468 | * @}
|
---|
469 | */
|
---|