source: mainline/uspace/drv/uhci-hcd/uhci.c@ 5f183dc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5f183dc was cabda7f, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

Minor fixes

initialize stack variables
use fixed size 32B address space
get rid of USE_INTERRUPTS macro
comment interrupt enabling code
reset hc before taking control
  • Property mode set to 100644
File size: 12.3 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup usb
29 * @{
30 */
31/** @file
32 * @brief UHCI driver
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "uhci.h"
45#include "iface.h"
46
47static irq_cmd_t uhci_cmds[] = {
48 {
49 .cmd = CMD_PIO_READ_16,
50 .addr = (void*)0xc022,
51 .dstarg = 1
52 },
53 {
54 .cmd = CMD_PIO_WRITE_16,
55 .addr = (void*)0xc022,
56 .value = 0x1f
57 },
58 {
59 .cmd = CMD_ACCEPT
60 }
61};
62
63
64static int usb_iface_get_address(ddf_fun_t *fun, devman_handle_t handle,
65 usb_address_t *address)
66{
67 assert(fun);
68 uhci_t *hc = fun_to_uhci(fun);
69 assert(hc);
70
71 usb_address_t addr = usb_address_keeping_find(&hc->address_manager,
72 handle);
73 if (addr < 0) {
74 return addr;
75 }
76
77 if (address != NULL) {
78 *address = addr;
79 }
80
81 return EOK;
82}
83/*----------------------------------------------------------------------------*/
84static usb_iface_t hc_usb_iface = {
85 .get_hc_handle = usb_iface_get_hc_handle_hc_impl,
86 .get_address = usb_iface_get_address
87};
88/*----------------------------------------------------------------------------*/
89static ddf_dev_ops_t uhci_ops = {
90 .interfaces[USB_DEV_IFACE] = &hc_usb_iface,
91 .interfaces[USBHC_DEV_IFACE] = &uhci_iface,
92};
93
94static int uhci_init_transfer_lists(uhci_t *instance);
95static int uhci_init_mem_structures(uhci_t *instance);
96static void uhci_init_hw(uhci_t *instance);
97
98static int uhci_interrupt_emulator(void *arg);
99static int uhci_debug_checker(void *arg);
100
101static bool allowed_usb_packet(
102 bool low_speed, usb_transfer_type_t, size_t size);
103
104#define CHECK_RET_RETURN(ret, message...) \
105 if (ret != EOK) { \
106 usb_log_error(message); \
107 return ret; \
108 } else (void) 0
109
110int uhci_init(uhci_t *instance, ddf_dev_t *dev, void *regs, size_t reg_size)
111{
112 assert(reg_size >= sizeof(regs_t));
113 int ret;
114
115 /*
116 * Create UHCI function.
117 */
118 instance->ddf_instance = ddf_fun_create(dev, fun_exposed, "uhci");
119 if (instance->ddf_instance == NULL) {
120 usb_log_error("Failed to create UHCI device function.\n");
121 return ENOMEM;
122 }
123 instance->ddf_instance->ops = &uhci_ops;
124 instance->ddf_instance->driver_data = instance;
125
126 ret = ddf_fun_bind(instance->ddf_instance);
127 CHECK_RET_RETURN(ret, "Failed to bind UHCI device function: %s.\n",
128 str_error(ret));
129
130 /* allow access to hc control registers */
131 regs_t *io;
132 ret = pio_enable(regs, reg_size, (void**)&io);
133 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p.\n", io);
134 instance->registers = io;
135 usb_log_debug("Device registers accessible.\n");
136
137 ret = uhci_init_mem_structures(instance);
138 CHECK_RET_RETURN(ret, "Failed to initialize memory structures.\n");
139
140 uhci_init_hw(instance);
141
142 instance->cleaner = fibril_create(uhci_interrupt_emulator, instance);
143 fibril_add_ready(instance->cleaner);
144
145 instance->debug_checker = fibril_create(uhci_debug_checker, instance);
146 fibril_add_ready(instance->debug_checker);
147
148 return EOK;
149}
150/*----------------------------------------------------------------------------*/
151void uhci_init_hw(uhci_t *instance)
152{
153 /* reset hc, who knows what touched it before us */
154 pio_write_16(&instance->registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
155 async_usleep(10000); /* 10ms according to USB spec */
156 pio_write_16(&instance->registers->usbcmd, 0);
157
158 /* set framelist pointer */
159 const uint32_t pa = addr_to_phys(instance->frame_list);
160 pio_write_32(&instance->registers->flbaseadd, pa);
161
162 /* enable all interrupts, but resume interrupt */
163// pio_write_16(&instance->registers->usbintr,
164// UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
165
166 /* Start the hc with large(64B) packet FSBR */
167 pio_write_16(&instance->registers->usbcmd,
168 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
169 usb_log_debug("Started UHCI HC.\n");
170}
171/*----------------------------------------------------------------------------*/
172int uhci_init_mem_structures(uhci_t *instance)
173{
174 assert(instance);
175
176 /* init interrupt code */
177 irq_cmd_t *interrupt_commands = malloc(sizeof(uhci_cmds));
178 if (interrupt_commands == NULL) {
179 return ENOMEM;
180 }
181 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
182 interrupt_commands[0].addr = (void*)&instance->registers->usbsts;
183 interrupt_commands[1].addr = (void*)&instance->registers->usbsts;
184 instance->interrupt_code.cmds = interrupt_commands;
185 instance->interrupt_code.cmdcount =
186 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
187
188 /* init transfer lists */
189 int ret = uhci_init_transfer_lists(instance);
190 CHECK_RET_RETURN(ret, "Failed to initialize transfer lists.\n");
191 usb_log_debug("Initialized transfer lists.\n");
192
193 /* frame list initialization */
194 instance->frame_list = get_page();
195 ret = instance ? EOK : ENOMEM;
196 CHECK_RET_RETURN(ret, "Failed to get frame list page.\n");
197 usb_log_debug("Initialized frame list.\n");
198
199 /* initialize all frames to point to the first queue head */
200 const uint32_t queue =
201 instance->transfers_interrupt.queue_head_pa
202 | LINK_POINTER_QUEUE_HEAD_FLAG;
203 unsigned i = 0;
204 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
205 instance->frame_list[i] = queue;
206 }
207
208 /* init address keeper(libusb) */
209 usb_address_keeping_init(&instance->address_manager, USB11_ADDRESS_MAX);
210 usb_log_debug("Initialized address manager.\n");
211
212 return EOK;
213}
214/*----------------------------------------------------------------------------*/
215int uhci_init_transfer_lists(uhci_t *instance)
216{
217 assert(instance);
218
219 /* initialize TODO: check errors */
220 int ret;
221 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
222 assert(ret == EOK);
223 ret = transfer_list_init(&instance->transfers_control_full, "CONTROL_FULL");
224 assert(ret == EOK);
225 ret = transfer_list_init(&instance->transfers_control_slow, "CONTROL_SLOW");
226 assert(ret == EOK);
227 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
228 assert(ret == EOK);
229
230 transfer_list_set_next(&instance->transfers_control_full,
231 &instance->transfers_bulk_full);
232 transfer_list_set_next(&instance->transfers_control_slow,
233 &instance->transfers_control_full);
234 transfer_list_set_next(&instance->transfers_interrupt,
235 &instance->transfers_control_slow);
236
237 /*FSBR*/
238#ifdef FSBR
239 transfer_list_set_next(&instance->transfers_bulk_full,
240 &instance->transfers_control_full);
241#endif
242
243 instance->transfers[0][USB_TRANSFER_INTERRUPT] =
244 &instance->transfers_interrupt;
245 instance->transfers[1][USB_TRANSFER_INTERRUPT] =
246 &instance->transfers_interrupt;
247 instance->transfers[0][USB_TRANSFER_CONTROL] =
248 &instance->transfers_control_full;
249 instance->transfers[1][USB_TRANSFER_CONTROL] =
250 &instance->transfers_control_slow;
251 instance->transfers[0][USB_TRANSFER_BULK] =
252 &instance->transfers_bulk_full;
253
254 return EOK;
255}
256/*----------------------------------------------------------------------------*/
257int uhci_schedule(uhci_t *instance, batch_t *batch)
258{
259 assert(instance);
260 assert(batch);
261 const int low_speed = (batch->speed == LOW_SPEED);
262 if (!allowed_usb_packet(
263 low_speed, batch->transfer_type, batch->max_packet_size)) {
264 usb_log_warning("Invalid USB packet specified %s SPEED %d %zu.\n",
265 low_speed ? "LOW" : "FULL" , batch->transfer_type,
266 batch->max_packet_size);
267 return ENOTSUP;
268 }
269 /* TODO: check available bandwith here */
270
271 transfer_list_t *list =
272 instance->transfers[low_speed][batch->transfer_type];
273 assert(list);
274 transfer_list_add_batch(list, batch);
275
276 return EOK;
277}
278/*----------------------------------------------------------------------------*/
279void uhci_interrupt(uhci_t *instance, uint16_t status)
280{
281 assert(instance);
282 if ((status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) == 0)
283 return;
284 usb_log_debug("UHCI interrupt: %X.\n", status);
285 transfer_list_check(&instance->transfers_interrupt);
286 transfer_list_check(&instance->transfers_control_slow);
287 transfer_list_check(&instance->transfers_control_full);
288 transfer_list_check(&instance->transfers_bulk_full);
289}
290/*----------------------------------------------------------------------------*/
291int uhci_interrupt_emulator(void* arg)
292{
293 usb_log_debug("Started interrupt emulator.\n");
294 uhci_t *instance = (uhci_t*)arg;
295 assert(instance);
296
297 while(1) {
298 uint16_t status = pio_read_16(&instance->registers->usbsts);
299 usb_log_debug("UHCI status: %x.\n", status);
300 status |= 1;
301 uhci_interrupt(instance, status);
302 pio_write_16(&instance->registers->usbsts, 0x1f);
303 async_usleep(UHCI_CLEANER_TIMEOUT * 1000);
304 }
305 return EOK;
306}
307/*---------------------------------------------------------------------------*/
308int uhci_debug_checker(void *arg)
309{
310 uhci_t *instance = (uhci_t*)arg;
311 assert(instance);
312 while (1) {
313 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
314 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
315 const uint16_t intr = pio_read_16(&instance->registers->usbintr);
316 usb_log_debug("Command: %X Status: %X Interrupts: %x\n",
317 cmd, sts, intr);
318
319 uintptr_t frame_list =
320 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
321 if (frame_list != addr_to_phys(instance->frame_list)) {
322 usb_log_debug("Framelist address: %p vs. %p.\n",
323 frame_list, addr_to_phys(instance->frame_list));
324 }
325 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
326 usb_log_debug2("Framelist item: %d \n", frnum );
327
328 queue_head_t* qh = instance->transfers_interrupt.queue_head;
329
330 if ((instance->frame_list[frnum] & (~0xf)) != (uintptr_t)addr_to_phys(qh)) {
331 usb_log_debug("Interrupt QH: %p vs. %p.\n",
332 instance->frame_list[frnum] & (~0xf), addr_to_phys(qh));
333 }
334
335 if ((qh->next_queue & (~0xf))
336 != (uintptr_t)addr_to_phys(instance->transfers_control_slow.queue_head)) {
337 usb_log_debug("Control Slow QH: %p vs. %p.\n", qh->next_queue & (~0xf),
338 addr_to_phys(instance->transfers_control_slow.queue_head));
339 }
340 qh = instance->transfers_control_slow.queue_head;
341
342 if ((qh->next_queue & (~0xf))
343 != (uintptr_t)addr_to_phys(instance->transfers_control_full.queue_head)) {
344 usb_log_debug("Control Full QH: %p vs. %p.\n", qh->next_queue & (~0xf),
345 addr_to_phys(instance->transfers_control_full.queue_head));\
346 }
347 qh = instance->transfers_control_full.queue_head;
348
349 if ((qh->next_queue & (~0xf))
350 != (uintptr_t)addr_to_phys(instance->transfers_bulk_full.queue_head)) {
351 usb_log_debug("Bulk QH: %p vs. %p.\n", qh->next_queue & (~0xf),
352 addr_to_phys(instance->transfers_bulk_full.queue_head));
353 }
354/*
355 uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
356 cmd |= UHCI_CMD_RUN_STOP;
357 pio_write_16(&instance->registers->usbcmd, cmd);
358*/
359 async_usleep(UHCI_DEBUGER_TIMEOUT);
360 }
361 return 0;
362}
363/*----------------------------------------------------------------------------*/
364bool allowed_usb_packet(
365 bool low_speed, usb_transfer_type_t transfer, size_t size)
366{
367 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
368 switch(transfer) {
369 case USB_TRANSFER_ISOCHRONOUS:
370 return (!low_speed && size < 1024);
371 case USB_TRANSFER_INTERRUPT:
372 return size <= (low_speed ? 8 : 64);
373 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
374 return (size <= (low_speed ? 8 : 64));
375 case USB_TRANSFER_BULK: /* device specifies its own max size */
376 return (!low_speed && size <= 64);
377 }
378 return false;
379}
380/**
381 * @}
382 */
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