source: mainline/uspace/drv/uhci-hcd/hc.c@ 6ce42e85

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6ce42e85 was 6ce42e85, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Use new usb_endpoint_manager instead of bandwidth_t

Bandwidth checks turned off for now.
  • Property mode set to 100644
File size: 17.6 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int hc_init_transfer_lists(hc_t *instance);
63static int hc_init_mem_structures(hc_t *instance);
64static void hc_init_hw(hc_t *instance);
65
66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
68
69static bool usb_is_allowed(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
72/** Initialize UHCI hcd driver structure
73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
83 */
84int hc_init(hc_t *instance, ddf_fun_t *fun,
85 void *regs, size_t reg_size, bool interrupts)
86{
87 assert(reg_size >= sizeof(regs_t));
88 int ret;
89
90#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
91 if (ret != EOK) { \
92 usb_log_error(message); \
93 if (instance->ddf_instance) \
94 ddf_fun_destroy(instance->ddf_instance); \
95 return ret; \
96 } else (void) 0
97
98 instance->hw_interrupts = interrupts;
99 instance->hw_failures = 0;
100
101 /* Setup UHCI function. */
102 instance->ddf_instance = fun;
103
104 /* allow access to hc control registers */
105 regs_t *io;
106 ret = pio_enable(regs, reg_size, (void**)&io);
107 CHECK_RET_DEST_FUN_RETURN(ret,
108 "Failed(%d) to gain access to registers at %p: %s.\n",
109 ret, str_error(ret), io);
110 instance->registers = io;
111 usb_log_debug("Device registers at %p(%u) accessible.\n",
112 io, reg_size);
113
114 ret = hc_init_mem_structures(instance);
115 CHECK_RET_DEST_FUN_RETURN(ret,
116 "Failed to initialize UHCI memory structures.\n");
117
118 hc_init_hw(instance);
119 if (!interrupts) {
120 instance->cleaner =
121 fibril_create(hc_interrupt_emulator, instance);
122 fibril_add_ready(instance->cleaner);
123 } else {
124 /* TODO: enable interrupts here */
125 }
126
127 instance->debug_checker =
128 fibril_create(hc_debug_checker, instance);
129// fibril_add_ready(instance->debug_checker);
130
131 return EOK;
132#undef CHECK_RET_DEST_FUN_RETURN
133}
134/*----------------------------------------------------------------------------*/
135/** Initialize UHCI hc hw resources.
136 *
137 * @param[in] instance UHCI structure to use.
138 * For magic values see UHCI Design Guide
139 */
140void hc_init_hw(hc_t *instance)
141{
142 assert(instance);
143 regs_t *registers = instance->registers;
144
145 /* Reset everything, who knows what touched it before us */
146 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
147 async_usleep(10000); /* 10ms according to USB spec */
148 pio_write_16(&registers->usbcmd, 0);
149
150 /* Reset hc, all states and counters */
151 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
152 do { async_usleep(10); }
153 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
154
155 /* Set frame to exactly 1ms */
156 pio_write_8(&registers->sofmod, 64);
157
158 /* Set frame list pointer */
159 const uint32_t pa = addr_to_phys(instance->frame_list);
160 pio_write_32(&registers->flbaseadd, pa);
161
162 if (instance->hw_interrupts) {
163 /* Enable all interrupts, but resume interrupt */
164 pio_write_16(&instance->registers->usbintr,
165 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
166 }
167
168 uint16_t status = pio_read_16(&registers->usbcmd);
169 if (status != 0)
170 usb_log_warning("Previous command value: %x.\n", status);
171
172 /* Start the hc with large(64B) packet FSBR */
173 pio_write_16(&registers->usbcmd,
174 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
175}
176/*----------------------------------------------------------------------------*/
177/** Initialize UHCI hc memory structures.
178 *
179 * @param[in] instance UHCI structure to use.
180 * @return Error code
181 * @note Should be called only once on any structure.
182 *
183 * Structures:
184 * - interrupt code (I/O addressses are customized per instance)
185 * - transfer lists (queue heads need to be accessible by the hw)
186 * - frame list page (needs to be one UHCI hw accessible 4K page)
187 */
188int hc_init_mem_structures(hc_t *instance)
189{
190 assert(instance);
191#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
192 if (ret != EOK) { \
193 usb_log_error(message); \
194 if (instance->interrupt_code.cmds != NULL) \
195 free(instance->interrupt_code.cmds); \
196 return ret; \
197 } else (void) 0
198
199 /* Init interrupt code */
200 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
201 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
202 CHECK_RET_DEST_CMDS_RETURN(ret,
203 "Failed to allocate interrupt cmds space.\n");
204
205 {
206 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
207 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
208 interrupt_commands[0].addr =
209 (void*)&instance->registers->usbsts;
210 interrupt_commands[1].addr =
211 (void*)&instance->registers->usbsts;
212 instance->interrupt_code.cmdcount =
213 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
214 }
215
216 /* Init transfer lists */
217 ret = hc_init_transfer_lists(instance);
218 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
219 usb_log_debug("Initialized transfer lists.\n");
220
221 /* Init USB frame list page*/
222 instance->frame_list = get_page();
223 ret = instance ? EOK : ENOMEM;
224 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
225 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
226
227 /* Set all frames to point to the first queue head */
228 const uint32_t queue =
229 instance->transfers_interrupt.queue_head_pa
230 | LINK_POINTER_QUEUE_HEAD_FLAG;
231
232 unsigned i = 0;
233 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
234 instance->frame_list[i] = queue;
235 }
236
237 /* Init device keeper*/
238 usb_device_keeper_init(&instance->manager);
239 usb_log_debug("Initialized device manager.\n");
240
241 ret =
242 usb_endpoint_manager_init(&instance->ep_manager,
243 BANDWIDTH_AVAILABLE_USB11);
244 assert(ret == EOK);
245
246 return EOK;
247#undef CHECK_RET_DEST_CMDS_RETURN
248}
249/*----------------------------------------------------------------------------*/
250/** Initialize UHCI hc transfer lists.
251 *
252 * @param[in] instance UHCI structure to use.
253 * @return Error code
254 * @note Should be called only once on any structure.
255 *
256 * Initializes transfer lists and sets them in one chain to support proper
257 * USB scheduling. Sets pointer table for quick access.
258 */
259int hc_init_transfer_lists(hc_t *instance)
260{
261 assert(instance);
262#define CHECK_RET_CLEAR_RETURN(ret, message...) \
263 if (ret != EOK) { \
264 usb_log_error(message); \
265 transfer_list_fini(&instance->transfers_bulk_full); \
266 transfer_list_fini(&instance->transfers_control_full); \
267 transfer_list_fini(&instance->transfers_control_slow); \
268 transfer_list_fini(&instance->transfers_interrupt); \
269 return ret; \
270 } else (void) 0
271
272 /* initialize TODO: check errors */
273 int ret;
274 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
275 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
276
277 ret = transfer_list_init(
278 &instance->transfers_control_full, "CONTROL_FULL");
279 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
280
281 ret = transfer_list_init(
282 &instance->transfers_control_slow, "CONTROL_SLOW");
283 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
284
285 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
286 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
287
288 transfer_list_set_next(&instance->transfers_control_full,
289 &instance->transfers_bulk_full);
290 transfer_list_set_next(&instance->transfers_control_slow,
291 &instance->transfers_control_full);
292 transfer_list_set_next(&instance->transfers_interrupt,
293 &instance->transfers_control_slow);
294
295 /*FSBR*/
296#ifdef FSBR
297 transfer_list_set_next(&instance->transfers_bulk_full,
298 &instance->transfers_control_full);
299#endif
300
301 /* Assign pointers to be used during scheduling */
302 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
303 &instance->transfers_interrupt;
304 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
305 &instance->transfers_interrupt;
306 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
307 &instance->transfers_control_full;
308 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
309 &instance->transfers_control_slow;
310 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
311 &instance->transfers_bulk_full;
312
313 return EOK;
314#undef CHECK_RET_CLEAR_RETURN
315}
316/*----------------------------------------------------------------------------*/
317/** Schedule batch for execution.
318 *
319 * @param[in] instance UHCI structure to use.
320 * @param[in] batch Transfer batch to schedule.
321 * @return Error code
322 *
323 * Checks for bandwidth availability and appends the batch to the proper queue.
324 */
325int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
326{
327 assert(instance);
328 assert(batch);
329 const int low_speed = (batch->speed == USB_SPEED_LOW);
330 if (!usb_is_allowed(
331 low_speed, batch->transfer_type, batch->max_packet_size)) {
332 usb_log_error("Invalid USB transfer specified %s %d %zu.\n",
333 usb_str_speed(batch->speed), batch->transfer_type,
334 batch->max_packet_size);
335 return ENOTSUP;
336 }
337 /* Check available bandwidth */
338/*
339 if (batch->transfer_type == USB_TRANSFER_INTERRUPT ||
340 batch->transfer_type == USB_TRANSFER_ISOCHRONOUS) {
341 const size_t bw = bandwidth_count_usb11(batch->speed,
342 batch->transfer_type, batch->buffer_size,
343 batch->max_packet_size);
344
345 int ret =
346 bandwidth_use(&instance->bandwidth, batch->target.address,
347 batch->target.endpoint, batch->direction, bw);
348 if (ret != EOK) {
349 usb_log_error("Failed(%d) to use reserved bw: %s.\n",
350 ret, str_error(ret));
351 return ret;
352 }
353 }
354*/
355
356 transfer_list_t *list =
357 instance->transfers[batch->speed][batch->transfer_type];
358 assert(list);
359 if (batch->transfer_type == USB_TRANSFER_CONTROL) {
360 usb_device_keeper_use_control(
361 &instance->manager, batch->target);
362 }
363 transfer_list_add_batch(list, batch);
364
365 return EOK;
366}
367/*----------------------------------------------------------------------------*/
368/** Take action based on the interrupt cause.
369 *
370 * @param[in] instance UHCI structure to use.
371 * @param[in] status Value of the status register at the time of interrupt.
372 *
373 * Interrupt might indicate:
374 * - transaction completed, either by triggering IOC, SPD, or an error
375 * - some kind of device error
376 * - resume from suspend state (not implemented)
377 */
378void hc_interrupt(hc_t *instance, uint16_t status)
379{
380 assert(instance);
381// status |= 1; //Uncomment to work around qemu hang
382 /* TODO: Resume interrupts are not supported */
383 /* Lower 2 bits are transaction error and transaction complete */
384 if (status & 0x3) {
385 LIST_INITIALIZE(done);
386 transfer_list_remove_finished(
387 &instance->transfers_interrupt, &done);
388 transfer_list_remove_finished(
389 &instance->transfers_control_slow, &done);
390 transfer_list_remove_finished(
391 &instance->transfers_control_full, &done);
392 transfer_list_remove_finished(
393 &instance->transfers_bulk_full, &done);
394
395 while (!list_empty(&done)) {
396 link_t *item = done.next;
397 list_remove(item);
398 usb_transfer_batch_t *batch =
399 list_get_instance(item, usb_transfer_batch_t, link);
400 switch (batch->transfer_type)
401 {
402 case USB_TRANSFER_CONTROL:
403 usb_device_keeper_release_control(
404 &instance->manager, batch->target);
405 break;
406 case USB_TRANSFER_INTERRUPT:
407 case USB_TRANSFER_ISOCHRONOUS: {
408/*
409 int ret = bandwidth_free(&instance->bandwidth,
410 batch->target.address,
411 batch->target.endpoint,
412 batch->direction);
413 if (ret != EOK)
414 usb_log_warning("Failed(%d) to free "
415 "reserved bw: %s.\n", ret,
416 str_error(ret));
417*/
418 }
419 default:
420 break;
421 }
422 batch->next_step(batch);
423 }
424 }
425 /* bits 4 and 5 indicate hc error */
426 if (status & 0x18) {
427 usb_log_error("UHCI hardware failure!.\n");
428 ++instance->hw_failures;
429 transfer_list_abort_all(&instance->transfers_interrupt);
430 transfer_list_abort_all(&instance->transfers_control_slow);
431 transfer_list_abort_all(&instance->transfers_control_full);
432 transfer_list_abort_all(&instance->transfers_bulk_full);
433
434 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
435 /* reinitialize hw, this triggers virtual disconnect*/
436 hc_init_hw(instance);
437 } else {
438 usb_log_fatal("Too many UHCI hardware failures!.\n");
439 hc_fini(instance);
440 }
441 }
442}
443/*----------------------------------------------------------------------------*/
444/** Polling function, emulates interrupts.
445 *
446 * @param[in] arg UHCI hc structure to use.
447 * @return EOK (should never return)
448 */
449int hc_interrupt_emulator(void* arg)
450{
451 usb_log_debug("Started interrupt emulator.\n");
452 hc_t *instance = (hc_t*)arg;
453 assert(instance);
454
455 while (1) {
456 /* read and ack interrupts */
457 uint16_t status = pio_read_16(&instance->registers->usbsts);
458 pio_write_16(&instance->registers->usbsts, 0x1f);
459 if (status != 0)
460 usb_log_debug2("UHCI status: %x.\n", status);
461 hc_interrupt(instance, status);
462 async_usleep(UHCI_CLEANER_TIMEOUT);
463 }
464 return EOK;
465}
466/*---------------------------------------------------------------------------*/
467/** Debug function, checks consistency of memory structures.
468 *
469 * @param[in] arg UHCI structure to use.
470 * @return EOK (should never return)
471 */
472int hc_debug_checker(void *arg)
473{
474 hc_t *instance = (hc_t*)arg;
475 assert(instance);
476
477#define QH(queue) \
478 instance->transfers_##queue.queue_head
479
480 while (1) {
481 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
482 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
483 const uint16_t intr =
484 pio_read_16(&instance->registers->usbintr);
485
486 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
487 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
488 cmd, sts, intr);
489 }
490
491 uintptr_t frame_list =
492 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
493 if (frame_list != addr_to_phys(instance->frame_list)) {
494 usb_log_debug("Framelist address: %p vs. %p.\n",
495 frame_list, addr_to_phys(instance->frame_list));
496 }
497
498 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
499
500 uintptr_t expected_pa = instance->frame_list[frnum]
501 & LINK_POINTER_ADDRESS_MASK;
502 uintptr_t real_pa = addr_to_phys(QH(interrupt));
503 if (expected_pa != real_pa) {
504 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
505 expected_pa, frnum, real_pa);
506 }
507
508 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
509 real_pa = addr_to_phys(QH(control_slow));
510 if (expected_pa != real_pa) {
511 usb_log_debug("Control Slow QH: %p vs. %p.\n",
512 expected_pa, real_pa);
513 }
514
515 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
516 real_pa = addr_to_phys(QH(control_full));
517 if (expected_pa != real_pa) {
518 usb_log_debug("Control Full QH: %p vs. %p.\n",
519 expected_pa, real_pa);
520 }
521
522 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
523 real_pa = addr_to_phys(QH(bulk_full));
524 if (expected_pa != real_pa ) {
525 usb_log_debug("Bulk QH: %p vs. %p.\n",
526 expected_pa, real_pa);
527 }
528 async_usleep(UHCI_DEBUGER_TIMEOUT);
529 }
530 return EOK;
531#undef QH
532}
533/*----------------------------------------------------------------------------*/
534/** Check transfers for USB validity
535 *
536 * @param[in] low_speed Transfer speed.
537 * @param[in] transfer Transer type
538 * @param[in] size Size of data packets
539 * @return True if transaction is allowed by USB specs, false otherwise
540 */
541bool usb_is_allowed(
542 bool low_speed, usb_transfer_type_t transfer, size_t size)
543{
544 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
545 switch(transfer)
546 {
547 case USB_TRANSFER_ISOCHRONOUS:
548 return (!low_speed && size < 1024);
549 case USB_TRANSFER_INTERRUPT:
550 return size <= (low_speed ? 8 : 64);
551 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
552 return (size <= (low_speed ? 8 : 64));
553 case USB_TRANSFER_BULK: /* device specifies its own max size */
554 return (!low_speed && size <= 64);
555 }
556 return false;
557}
558/**
559 * @}
560 */
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