source: mainline/uspace/drv/uhci-hcd/hc.c@ 3476be8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3476be8 was d2bff2f, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

UHCI refactoring
  • Property mode set to 100644
File size: 15.4 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "hc.h"
45
46#define UHCI_INTR_ALLOW_INTERRUPTS \
47 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
48#define UHCI_STATUS_USED_INTERRUPTS \
49 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
50
51
52static int hc_init_transfer_lists(hc_t *instance);
53static int hc_init_mem_structures(hc_t *instance);
54static void hc_init_hw(hc_t *instance);
55
56static int hc_interrupt_emulator(void *arg);
57static int hc_debug_checker(void *arg);
58/*----------------------------------------------------------------------------*/
59/** Initialize UHCI hcd driver structure
60 *
61 * @param[in] instance Memory place to initialize.
62 * @param[in] regs Address of I/O control registers.
63 * @param[in] size Size of I/O control registers.
64 * @return Error code.
65 * @note Should be called only once on any structure.
66 *
67 * Initializes memory structures, starts up hw, and launches debugger and
68 * interrupt fibrils.
69 */
70int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
71{
72 assert(reg_size >= sizeof(regs_t));
73 int ret;
74
75#define CHECK_RET_RETURN(ret, message...) \
76 if (ret != EOK) { \
77 usb_log_error(message); \
78 return ret; \
79 } else (void) 0
80
81 instance->hw_interrupts = interrupts;
82 instance->hw_failures = 0;
83
84 /* allow access to hc control registers */
85 regs_t *io;
86 ret = pio_enable(regs, reg_size, (void**)&io);
87 CHECK_RET_RETURN(ret,
88 "Failed(%d) to gain access to registers at %p: %s.\n",
89 ret, io, str_error(ret));
90 instance->registers = io;
91 usb_log_debug("Device registers at %p (%zuB) accessible.\n",
92 io, reg_size);
93
94 ret = hc_init_mem_structures(instance);
95 CHECK_RET_RETURN(ret,
96 "Failed(%d) to initialize UHCI memory structures: %s.\n",
97 ret, str_error(ret));
98
99 hc_init_hw(instance);
100 if (!interrupts) {
101 instance->interrupt_emulator =
102 fibril_create(hc_interrupt_emulator, instance);
103 fibril_add_ready(instance->interrupt_emulator);
104 }
105 (void)hc_debug_checker;
106
107 return EOK;
108#undef CHECK_RET_DEST_FUN_RETURN
109}
110/*----------------------------------------------------------------------------*/
111/** Initialize UHCI hc hw resources.
112 *
113 * @param[in] instance UHCI structure to use.
114 * For magic values see UHCI Design Guide
115 */
116void hc_init_hw(hc_t *instance)
117{
118 assert(instance);
119 regs_t *registers = instance->registers;
120
121 /* Reset everything, who knows what touched it before us */
122 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
123 async_usleep(10000); /* 10ms according to USB spec */
124 pio_write_16(&registers->usbcmd, 0);
125
126 /* Reset hc, all states and counters */
127 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
128 do { async_usleep(10); }
129 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
130
131 /* Set frame to exactly 1ms */
132 pio_write_8(&registers->sofmod, 64);
133
134 /* Set frame list pointer */
135 const uint32_t pa = addr_to_phys(instance->frame_list);
136 pio_write_32(&registers->flbaseadd, pa);
137
138 if (instance->hw_interrupts) {
139 /* Enable all interrupts, but resume interrupt */
140 pio_write_16(&instance->registers->usbintr,
141 UHCI_INTR_ALLOW_INTERRUPTS);
142 }
143
144 uint16_t status = pio_read_16(&registers->usbcmd);
145 if (status != 0)
146 usb_log_warning("Previous command value: %x.\n", status);
147
148 /* Start the hc with large(64B) packet FSBR */
149 pio_write_16(&registers->usbcmd,
150 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
151}
152/*----------------------------------------------------------------------------*/
153/** Initialize UHCI hc memory structures.
154 *
155 * @param[in] instance UHCI structure to use.
156 * @return Error code
157 * @note Should be called only once on any structure.
158 *
159 * Structures:
160 * - interrupt code (I/O addressses are customized per instance)
161 * - transfer lists (queue heads need to be accessible by the hw)
162 * - frame list page (needs to be one UHCI hw accessible 4K page)
163 */
164int hc_init_mem_structures(hc_t *instance)
165{
166 assert(instance);
167#define CHECK_RET_RETURN(ret, message...) \
168 if (ret != EOK) { \
169 usb_log_error(message); \
170 return ret; \
171 } else (void) 0
172
173 /* Init interrupt code */
174 instance->interrupt_code.cmds = instance->interrupt_commands;
175 {
176 /* Read status register */
177 instance->interrupt_commands[0].cmd = CMD_PIO_READ_16;
178 instance->interrupt_commands[0].dstarg = 1;
179 instance->interrupt_commands[0].addr =
180 &instance->registers->usbsts;
181
182 /* Test whether we are the interrupt cause */
183 instance->interrupt_commands[1].cmd = CMD_BTEST;
184 instance->interrupt_commands[1].value =
185 UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS;
186 instance->interrupt_commands[1].srcarg = 1;
187 instance->interrupt_commands[1].dstarg = 2;
188
189 /* Predicate cleaning and accepting */
190 instance->interrupt_commands[2].cmd = CMD_PREDICATE;
191 instance->interrupt_commands[2].value = 2;
192 instance->interrupt_commands[2].srcarg = 2;
193
194 /* Write clean status register */
195 instance->interrupt_commands[3].cmd = CMD_PIO_WRITE_A_16;
196 instance->interrupt_commands[3].srcarg = 1;
197 instance->interrupt_commands[3].addr =
198 &instance->registers->usbsts;
199
200 /* Accept interrupt */
201 instance->interrupt_commands[4].cmd = CMD_ACCEPT;
202
203 instance->interrupt_code.cmdcount = UHCI_NEEDED_IRQ_COMMANDS;
204 }
205
206 /* Init transfer lists */
207 int ret = hc_init_transfer_lists(instance);
208 CHECK_RET_RETURN(ret, "Failed to init transfer lists.\n");
209 usb_log_debug("Initialized transfer lists.\n");
210
211 /* Init USB frame list page*/
212 instance->frame_list = get_page();
213 ret = instance ? EOK : ENOMEM;
214 CHECK_RET_RETURN(ret, "Failed to get frame list page.\n");
215 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
216
217 /* Set all frames to point to the first queue head */
218 const uint32_t queue = LINK_POINTER_QH(
219 addr_to_phys(instance->transfers_interrupt.queue_head));
220
221 unsigned i = 0;
222 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
223 instance->frame_list[i] = queue;
224 }
225
226 /* Init device keeper */
227 usb_device_keeper_init(&instance->manager);
228 usb_log_debug("Initialized device manager.\n");
229
230 ret = usb_endpoint_manager_init(&instance->ep_manager,
231 BANDWIDTH_AVAILABLE_USB11);
232 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
233 str_error(ret));
234
235 return EOK;
236#undef CHECK_RET_RETURN
237}
238/*----------------------------------------------------------------------------*/
239/** Initialize UHCI hc transfer lists.
240 *
241 * @param[in] instance UHCI structure to use.
242 * @return Error code
243 * @note Should be called only once on any structure.
244 *
245 * Initializes transfer lists and sets them in one chain to support proper
246 * USB scheduling. Sets pointer table for quick access.
247 */
248int hc_init_transfer_lists(hc_t *instance)
249{
250 assert(instance);
251#define SETUP_TRANSFER_LIST(type, name) \
252do { \
253 int ret = transfer_list_init(&instance->transfers_##type, name); \
254 if (ret != EOK) { \
255 usb_log_error("Failed(%d) to setup %s transfer list: %s.\n", \
256 ret, name, str_error(ret)); \
257 transfer_list_fini(&instance->transfers_bulk_full); \
258 transfer_list_fini(&instance->transfers_control_full); \
259 transfer_list_fini(&instance->transfers_control_slow); \
260 transfer_list_fini(&instance->transfers_interrupt); \
261 return ret; \
262 } \
263} while (0)
264
265 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
266 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
267 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
268 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
269#undef SETUP_TRANSFER_LIST
270 /* Connect lists into one schedule */
271 transfer_list_set_next(&instance->transfers_control_full,
272 &instance->transfers_bulk_full);
273 transfer_list_set_next(&instance->transfers_control_slow,
274 &instance->transfers_control_full);
275 transfer_list_set_next(&instance->transfers_interrupt,
276 &instance->transfers_control_slow);
277
278 /*FSBR*/
279#ifdef FSBR
280 transfer_list_set_next(&instance->transfers_bulk_full,
281 &instance->transfers_control_full);
282#endif
283
284 /* Assign pointers to be used during scheduling */
285 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
286 &instance->transfers_interrupt;
287 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
288 &instance->transfers_interrupt;
289 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
290 &instance->transfers_control_full;
291 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
292 &instance->transfers_control_slow;
293 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
294 &instance->transfers_bulk_full;
295
296 return EOK;
297#undef CHECK_RET_CLEAR_RETURN
298}
299/*----------------------------------------------------------------------------*/
300/** Schedule batch for execution.
301 *
302 * @param[in] instance UHCI structure to use.
303 * @param[in] batch Transfer batch to schedule.
304 * @return Error code
305 *
306 * Checks for bandwidth availability and appends the batch to the proper queue.
307 */
308int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
309{
310 assert(instance);
311 assert(batch);
312
313 transfer_list_t *list =
314 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
315 assert(list);
316 transfer_list_add_batch(list, batch);
317
318 return EOK;
319}
320/*----------------------------------------------------------------------------*/
321/** Take action based on the interrupt cause.
322 *
323 * @param[in] instance UHCI structure to use.
324 * @param[in] status Value of the status register at the time of interrupt.
325 *
326 * Interrupt might indicate:
327 * - transaction completed, either by triggering IOC, SPD, or an error
328 * - some kind of device error
329 * - resume from suspend state (not implemented)
330 */
331void hc_interrupt(hc_t *instance, uint16_t status)
332{
333 assert(instance);
334 /* Lower 2 bits are transaction error and transaction complete */
335 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
336 LIST_INITIALIZE(done);
337 transfer_list_remove_finished(
338 &instance->transfers_interrupt, &done);
339 transfer_list_remove_finished(
340 &instance->transfers_control_slow, &done);
341 transfer_list_remove_finished(
342 &instance->transfers_control_full, &done);
343 transfer_list_remove_finished(
344 &instance->transfers_bulk_full, &done);
345
346 while (!list_empty(&done)) {
347 link_t *item = done.next;
348 list_remove(item);
349 usb_transfer_batch_t *batch =
350 list_get_instance(item, usb_transfer_batch_t, link);
351 usb_transfer_batch_finish(batch);
352 }
353 }
354 /* Resume interrupts are not supported */
355 if (status & UHCI_STATUS_RESUME) {
356 usb_log_error("Resume interrupt!\n");
357 }
358
359 /* Bits 4 and 5 indicate hc error */
360 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
361 usb_log_error("UHCI hardware failure!.\n");
362 ++instance->hw_failures;
363 transfer_list_abort_all(&instance->transfers_interrupt);
364 transfer_list_abort_all(&instance->transfers_control_slow);
365 transfer_list_abort_all(&instance->transfers_control_full);
366 transfer_list_abort_all(&instance->transfers_bulk_full);
367
368 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
369 /* reinitialize hw, this triggers virtual disconnect*/
370 hc_init_hw(instance);
371 } else {
372 usb_log_fatal("Too many UHCI hardware failures!.\n");
373 hc_fini(instance);
374 }
375 }
376}
377/*----------------------------------------------------------------------------*/
378/** Polling function, emulates interrupts.
379 *
380 * @param[in] arg UHCI hc structure to use.
381 * @return EOK (should never return)
382 */
383int hc_interrupt_emulator(void* arg)
384{
385 usb_log_debug("Started interrupt emulator.\n");
386 hc_t *instance = arg;
387 assert(instance);
388
389 while (1) {
390 /* Read and clear status register */
391 uint16_t status = pio_read_16(&instance->registers->usbsts);
392 pio_write_16(&instance->registers->usbsts, status);
393 if (status != 0)
394 usb_log_debug2("UHCI status: %x.\n", status);
395// Qemu fails to report stalled communication
396// see https://bugs.launchpad.net/qemu/+bug/757654
397// This is a simple workaround to force queue processing every time
398 // status |= 1;
399 hc_interrupt(instance, status);
400 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
401 }
402 return EOK;
403}
404/*---------------------------------------------------------------------------*/
405/** Debug function, checks consistency of memory structures.
406 *
407 * @param[in] arg UHCI structure to use.
408 * @return EOK (should never return)
409 */
410int hc_debug_checker(void *arg)
411{
412 hc_t *instance = arg;
413 assert(instance);
414
415#define QH(queue) \
416 instance->transfers_##queue.queue_head
417
418 while (1) {
419 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
420 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
421 const uint16_t intr =
422 pio_read_16(&instance->registers->usbintr);
423
424 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
425 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
426 cmd, sts, intr);
427 }
428
429 uintptr_t frame_list =
430 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
431 if (frame_list != addr_to_phys(instance->frame_list)) {
432 usb_log_debug("Framelist address: %p vs. %p.\n",
433 (void *) frame_list,
434 (void *) addr_to_phys(instance->frame_list));
435 }
436
437 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
438
439 uintptr_t expected_pa = instance->frame_list[frnum]
440 & LINK_POINTER_ADDRESS_MASK;
441 uintptr_t real_pa = addr_to_phys(QH(interrupt));
442 if (expected_pa != real_pa) {
443 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
444 (void *) expected_pa, frnum, (void *) real_pa);
445 }
446
447 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
448 real_pa = addr_to_phys(QH(control_slow));
449 if (expected_pa != real_pa) {
450 usb_log_debug("Control Slow QH: %p vs. %p.\n",
451 (void *) expected_pa, (void *) real_pa);
452 }
453
454 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
455 real_pa = addr_to_phys(QH(control_full));
456 if (expected_pa != real_pa) {
457 usb_log_debug("Control Full QH: %p vs. %p.\n",
458 (void *) expected_pa, (void *) real_pa);
459 }
460
461 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
462 real_pa = addr_to_phys(QH(bulk_full));
463 if (expected_pa != real_pa ) {
464 usb_log_debug("Bulk QH: %p vs. %p.\n",
465 (void *) expected_pa, (void *) real_pa);
466 }
467 async_usleep(UHCI_DEBUGER_TIMEOUT);
468 }
469 return EOK;
470#undef QH
471}
472/**
473 * @}
474 */
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