source: mainline/uspace/drv/uhci-hcd/hc.c@ 28d9c95

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 28d9c95 was 23f40280, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "hc.h"
45
46#define UHCI_INTR_ALLOW_INTERRUPTS \
47 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
48#define UHCI_STATUS_USED_INTERRUPTS \
49 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
50
51
52static int hc_init_transfer_lists(hc_t *instance);
53static int hc_init_mem_structures(hc_t *instance);
54static void hc_init_hw(hc_t *instance);
55
56static int hc_interrupt_emulator(void *arg);
57static int hc_debug_checker(void *arg);
58/*----------------------------------------------------------------------------*/
59/** Initialize UHCI hcd driver structure
60 *
61 * @param[in] instance Memory place to initialize.
62 * @param[in] regs Address of I/O control registers.
63 * @param[in] reg_size Size of I/O control registers.
64 * @param[in] interrupts True if hw interrupts should be used.
65 * @return Error code.
66 * @note Should be called only once on any structure.
67 *
68 * Initializes memory structures, starts up hw, and launches debugger and
69 * interrupt fibrils.
70 */
71int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
72{
73 assert(reg_size >= sizeof(regs_t));
74 int ret;
75
76#define CHECK_RET_RETURN(ret, message...) \
77 if (ret != EOK) { \
78 usb_log_error(message); \
79 return ret; \
80 } else (void) 0
81
82 instance->hw_interrupts = interrupts;
83 instance->hw_failures = 0;
84
85 /* allow access to hc control registers */
86 regs_t *io;
87 ret = pio_enable(regs, reg_size, (void**)&io);
88 CHECK_RET_RETURN(ret,
89 "Failed(%d) to gain access to registers at %p: %s.\n",
90 ret, io, str_error(ret));
91 instance->registers = io;
92 usb_log_debug("Device registers at %p (%zuB) accessible.\n",
93 io, reg_size);
94
95 ret = hc_init_mem_structures(instance);
96 CHECK_RET_RETURN(ret,
97 "Failed(%d) to initialize UHCI memory structures: %s.\n",
98 ret, str_error(ret));
99
100 hc_init_hw(instance);
101 if (!interrupts) {
102 instance->interrupt_emulator =
103 fibril_create(hc_interrupt_emulator, instance);
104 fibril_add_ready(instance->interrupt_emulator);
105 }
106 (void)hc_debug_checker;
107
108 return EOK;
109#undef CHECK_RET_DEST_FUN_RETURN
110}
111/*----------------------------------------------------------------------------*/
112/** Initialize UHCI hc hw resources.
113 *
114 * @param[in] instance UHCI structure to use.
115 * For magic values see UHCI Design Guide
116 */
117void hc_init_hw(hc_t *instance)
118{
119 assert(instance);
120 regs_t *registers = instance->registers;
121
122 /* Reset everything, who knows what touched it before us */
123 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
124 async_usleep(10000); /* 10ms according to USB spec */
125 pio_write_16(&registers->usbcmd, 0);
126
127 /* Reset hc, all states and counters */
128 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
129 do { async_usleep(10); }
130 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
131
132 /* Set frame to exactly 1ms */
133 pio_write_8(&registers->sofmod, 64);
134
135 /* Set frame list pointer */
136 const uint32_t pa = addr_to_phys(instance->frame_list);
137 pio_write_32(&registers->flbaseadd, pa);
138
139 if (instance->hw_interrupts) {
140 /* Enable all interrupts, but resume interrupt */
141 pio_write_16(&instance->registers->usbintr,
142 UHCI_INTR_ALLOW_INTERRUPTS);
143 }
144
145 uint16_t status = pio_read_16(&registers->usbcmd);
146 if (status != 0)
147 usb_log_warning("Previous command value: %x.\n", status);
148
149 /* Start the hc with large(64B) packet FSBR */
150 pio_write_16(&registers->usbcmd,
151 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
152}
153/*----------------------------------------------------------------------------*/
154/** Initialize UHCI hc memory structures.
155 *
156 * @param[in] instance UHCI structure to use.
157 * @return Error code
158 * @note Should be called only once on any structure.
159 *
160 * Structures:
161 * - interrupt code (I/O addressses are customized per instance)
162 * - transfer lists (queue heads need to be accessible by the hw)
163 * - frame list page (needs to be one UHCI hw accessible 4K page)
164 */
165int hc_init_mem_structures(hc_t *instance)
166{
167 assert(instance);
168#define CHECK_RET_RETURN(ret, message...) \
169 if (ret != EOK) { \
170 usb_log_error(message); \
171 return ret; \
172 } else (void) 0
173
174 /* Init interrupt code */
175 instance->interrupt_code.cmds = instance->interrupt_commands;
176 {
177 /* Read status register */
178 instance->interrupt_commands[0].cmd = CMD_PIO_READ_16;
179 instance->interrupt_commands[0].dstarg = 1;
180 instance->interrupt_commands[0].addr =
181 &instance->registers->usbsts;
182
183 /* Test whether we are the interrupt cause */
184 instance->interrupt_commands[1].cmd = CMD_BTEST;
185 instance->interrupt_commands[1].value =
186 UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS;
187 instance->interrupt_commands[1].srcarg = 1;
188 instance->interrupt_commands[1].dstarg = 2;
189
190 /* Predicate cleaning and accepting */
191 instance->interrupt_commands[2].cmd = CMD_PREDICATE;
192 instance->interrupt_commands[2].value = 2;
193 instance->interrupt_commands[2].srcarg = 2;
194
195 /* Write clean status register */
196 instance->interrupt_commands[3].cmd = CMD_PIO_WRITE_A_16;
197 instance->interrupt_commands[3].srcarg = 1;
198 instance->interrupt_commands[3].addr =
199 &instance->registers->usbsts;
200
201 /* Accept interrupt */
202 instance->interrupt_commands[4].cmd = CMD_ACCEPT;
203
204 instance->interrupt_code.cmdcount = UHCI_NEEDED_IRQ_COMMANDS;
205 }
206
207 /* Init transfer lists */
208 int ret = hc_init_transfer_lists(instance);
209 CHECK_RET_RETURN(ret, "Failed to init transfer lists.\n");
210 usb_log_debug("Initialized transfer lists.\n");
211
212 /* Init USB frame list page*/
213 instance->frame_list = get_page();
214 ret = instance ? EOK : ENOMEM;
215 CHECK_RET_RETURN(ret, "Failed to get frame list page.\n");
216 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
217
218 /* Set all frames to point to the first queue head */
219 const uint32_t queue = LINK_POINTER_QH(
220 addr_to_phys(instance->transfers_interrupt.queue_head));
221
222 unsigned i = 0;
223 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
224 instance->frame_list[i] = queue;
225 }
226
227 /* Init device keeper */
228 usb_device_keeper_init(&instance->manager);
229 usb_log_debug("Initialized device manager.\n");
230
231 ret = usb_endpoint_manager_init(&instance->ep_manager,
232 BANDWIDTH_AVAILABLE_USB11);
233 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
234 str_error(ret));
235
236 return EOK;
237#undef CHECK_RET_RETURN
238}
239/*----------------------------------------------------------------------------*/
240/** Initialize UHCI hc transfer lists.
241 *
242 * @param[in] instance UHCI structure to use.
243 * @return Error code
244 * @note Should be called only once on any structure.
245 *
246 * Initializes transfer lists and sets them in one chain to support proper
247 * USB scheduling. Sets pointer table for quick access.
248 */
249int hc_init_transfer_lists(hc_t *instance)
250{
251 assert(instance);
252#define SETUP_TRANSFER_LIST(type, name) \
253do { \
254 int ret = transfer_list_init(&instance->transfers_##type, name); \
255 if (ret != EOK) { \
256 usb_log_error("Failed(%d) to setup %s transfer list: %s.\n", \
257 ret, name, str_error(ret)); \
258 transfer_list_fini(&instance->transfers_bulk_full); \
259 transfer_list_fini(&instance->transfers_control_full); \
260 transfer_list_fini(&instance->transfers_control_slow); \
261 transfer_list_fini(&instance->transfers_interrupt); \
262 return ret; \
263 } \
264} while (0)
265
266 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
267 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
268 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
269 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
270#undef SETUP_TRANSFER_LIST
271 /* Connect lists into one schedule */
272 transfer_list_set_next(&instance->transfers_control_full,
273 &instance->transfers_bulk_full);
274 transfer_list_set_next(&instance->transfers_control_slow,
275 &instance->transfers_control_full);
276 transfer_list_set_next(&instance->transfers_interrupt,
277 &instance->transfers_control_slow);
278
279 /*FSBR*/
280#ifdef FSBR
281 transfer_list_set_next(&instance->transfers_bulk_full,
282 &instance->transfers_control_full);
283#endif
284
285 /* Assign pointers to be used during scheduling */
286 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
287 &instance->transfers_interrupt;
288 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
289 &instance->transfers_interrupt;
290 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
291 &instance->transfers_control_full;
292 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
293 &instance->transfers_control_slow;
294 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
295 &instance->transfers_bulk_full;
296
297 return EOK;
298#undef CHECK_RET_CLEAR_RETURN
299}
300/*----------------------------------------------------------------------------*/
301/** Schedule batch for execution.
302 *
303 * @param[in] instance UHCI structure to use.
304 * @param[in] batch Transfer batch to schedule.
305 * @return Error code
306 *
307 * Checks for bandwidth availability and appends the batch to the proper queue.
308 */
309int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
310{
311 assert(instance);
312 assert(batch);
313
314 transfer_list_t *list =
315 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
316 assert(list);
317 transfer_list_add_batch(list, batch);
318
319 return EOK;
320}
321/*----------------------------------------------------------------------------*/
322/** Take action based on the interrupt cause.
323 *
324 * @param[in] instance UHCI structure to use.
325 * @param[in] status Value of the status register at the time of interrupt.
326 *
327 * Interrupt might indicate:
328 * - transaction completed, either by triggering IOC, SPD, or an error
329 * - some kind of device error
330 * - resume from suspend state (not implemented)
331 */
332void hc_interrupt(hc_t *instance, uint16_t status)
333{
334 assert(instance);
335 /* Lower 2 bits are transaction error and transaction complete */
336 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
337 LIST_INITIALIZE(done);
338 transfer_list_remove_finished(
339 &instance->transfers_interrupt, &done);
340 transfer_list_remove_finished(
341 &instance->transfers_control_slow, &done);
342 transfer_list_remove_finished(
343 &instance->transfers_control_full, &done);
344 transfer_list_remove_finished(
345 &instance->transfers_bulk_full, &done);
346
347 while (!list_empty(&done)) {
348 link_t *item = done.next;
349 list_remove(item);
350 usb_transfer_batch_t *batch =
351 list_get_instance(item, usb_transfer_batch_t, link);
352 usb_transfer_batch_finish(batch);
353 }
354 }
355 /* Resume interrupts are not supported */
356 if (status & UHCI_STATUS_RESUME) {
357 usb_log_error("Resume interrupt!\n");
358 }
359
360 /* Bits 4 and 5 indicate hc error */
361 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
362 usb_log_error("UHCI hardware failure!.\n");
363 ++instance->hw_failures;
364 transfer_list_abort_all(&instance->transfers_interrupt);
365 transfer_list_abort_all(&instance->transfers_control_slow);
366 transfer_list_abort_all(&instance->transfers_control_full);
367 transfer_list_abort_all(&instance->transfers_bulk_full);
368
369 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
370 /* reinitialize hw, this triggers virtual disconnect*/
371 hc_init_hw(instance);
372 } else {
373 usb_log_fatal("Too many UHCI hardware failures!.\n");
374 hc_fini(instance);
375 }
376 }
377}
378/*----------------------------------------------------------------------------*/
379/** Polling function, emulates interrupts.
380 *
381 * @param[in] arg UHCI hc structure to use.
382 * @return EOK (should never return)
383 */
384int hc_interrupt_emulator(void* arg)
385{
386 usb_log_debug("Started interrupt emulator.\n");
387 hc_t *instance = arg;
388 assert(instance);
389
390 while (1) {
391 /* Read and clear status register */
392 uint16_t status = pio_read_16(&instance->registers->usbsts);
393 pio_write_16(&instance->registers->usbsts, status);
394 if (status != 0)
395 usb_log_debug2("UHCI status: %x.\n", status);
396// Qemu fails to report stalled communication
397// see https://bugs.launchpad.net/qemu/+bug/757654
398// This is a simple workaround to force queue processing every time
399 // status |= 1;
400 hc_interrupt(instance, status);
401 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
402 }
403 return EOK;
404}
405/*---------------------------------------------------------------------------*/
406/** Debug function, checks consistency of memory structures.
407 *
408 * @param[in] arg UHCI structure to use.
409 * @return EOK (should never return)
410 */
411int hc_debug_checker(void *arg)
412{
413 hc_t *instance = arg;
414 assert(instance);
415
416#define QH(queue) \
417 instance->transfers_##queue.queue_head
418
419 while (1) {
420 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
421 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
422 const uint16_t intr =
423 pio_read_16(&instance->registers->usbintr);
424
425 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
426 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
427 cmd, sts, intr);
428 }
429
430 uintptr_t frame_list =
431 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
432 if (frame_list != addr_to_phys(instance->frame_list)) {
433 usb_log_debug("Framelist address: %p vs. %p.\n",
434 (void *) frame_list,
435 (void *) addr_to_phys(instance->frame_list));
436 }
437
438 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
439
440 uintptr_t expected_pa = instance->frame_list[frnum]
441 & LINK_POINTER_ADDRESS_MASK;
442 uintptr_t real_pa = addr_to_phys(QH(interrupt));
443 if (expected_pa != real_pa) {
444 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
445 (void *) expected_pa, frnum, (void *) real_pa);
446 }
447
448 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
449 real_pa = addr_to_phys(QH(control_slow));
450 if (expected_pa != real_pa) {
451 usb_log_debug("Control Slow QH: %p vs. %p.\n",
452 (void *) expected_pa, (void *) real_pa);
453 }
454
455 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
456 real_pa = addr_to_phys(QH(control_full));
457 if (expected_pa != real_pa) {
458 usb_log_debug("Control Full QH: %p vs. %p.\n",
459 (void *) expected_pa, (void *) real_pa);
460 }
461
462 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
463 real_pa = addr_to_phys(QH(bulk_full));
464 if (expected_pa != real_pa ) {
465 usb_log_debug("Bulk QH: %p vs. %p.\n",
466 (void *) expected_pa, (void *) real_pa);
467 }
468 async_usleep(UHCI_DEBUGER_TIMEOUT);
469 }
470 return EOK;
471#undef QH
472}
473/**
474 * @}
475 */
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