source: mainline/uspace/drv/uhci-hcd/hc.c@ 049a16f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 049a16f was 563ead9, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Further cleanup, includes, const, …
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File size: 15.5 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43
44#define UHCI_INTR_ALLOW_INTERRUPTS \
45 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
46#define UHCI_STATUS_USED_INTERRUPTS \
47 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
48
49
50static int hc_init_transfer_lists(hc_t *instance);
51static int hc_init_mem_structures(hc_t *instance);
52static void hc_init_hw(hc_t *instance);
53
54static int hc_interrupt_emulator(void *arg);
55static int hc_debug_checker(void *arg);
56/*----------------------------------------------------------------------------*/
57/** Initialize UHCI hc driver structure
58 *
59 * @param[in] instance Memory place to initialize.
60 * @param[in] regs Address of I/O control registers.
61 * @param[in] reg_size Size of I/O control registers.
62 * @param[in] interrupts True if hw interrupts should be used.
63 * @return Error code.
64 * @note Should be called only once on any structure.
65 *
66 * Initializes memory structures, starts up hw, and launches debugger and
67 * interrupt fibrils.
68 */
69int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
70{
71 assert(reg_size >= sizeof(regs_t));
72 int ret;
73
74#define CHECK_RET_RETURN(ret, message...) \
75 if (ret != EOK) { \
76 usb_log_error(message); \
77 return ret; \
78 } else (void) 0
79
80 instance->hw_interrupts = interrupts;
81 instance->hw_failures = 0;
82
83 /* allow access to hc control registers */
84 regs_t *io;
85 ret = pio_enable(regs, reg_size, (void **)&io);
86 CHECK_RET_RETURN(ret,
87 "Failed(%d) to gain access to registers at %p: %s.\n",
88 ret, io, str_error(ret));
89 instance->registers = io;
90 usb_log_debug("Device registers at %p (%zuB) accessible.\n",
91 io, reg_size);
92
93 ret = hc_init_mem_structures(instance);
94 CHECK_RET_RETURN(ret,
95 "Failed(%d) to initialize UHCI memory structures: %s.\n",
96 ret, str_error(ret));
97
98 hc_init_hw(instance);
99 if (!interrupts) {
100 instance->interrupt_emulator =
101 fibril_create(hc_interrupt_emulator, instance);
102 fibril_add_ready(instance->interrupt_emulator);
103 }
104 (void)hc_debug_checker;
105
106 return EOK;
107#undef CHECK_RET_DEST_FUN_RETURN
108}
109/*----------------------------------------------------------------------------*/
110/** Initialize UHCI hc hw resources.
111 *
112 * @param[in] instance UHCI structure to use.
113 * For magic values see UHCI Design Guide
114 */
115void hc_init_hw(hc_t *instance)
116{
117 assert(instance);
118 regs_t *registers = instance->registers;
119
120 /* Reset everything, who knows what touched it before us */
121 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
122 async_usleep(10000); /* 10ms according to USB spec */
123 pio_write_16(&registers->usbcmd, 0);
124
125 /* Reset hc, all states and counters */
126 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
127 do { async_usleep(10); }
128 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
129
130 /* Set frame to exactly 1ms */
131 pio_write_8(&registers->sofmod, 64);
132
133 /* Set frame list pointer */
134 const uint32_t pa = addr_to_phys(instance->frame_list);
135 pio_write_32(&registers->flbaseadd, pa);
136
137 if (instance->hw_interrupts) {
138 /* Enable all interrupts, but resume interrupt */
139 pio_write_16(&instance->registers->usbintr,
140 UHCI_INTR_ALLOW_INTERRUPTS);
141 }
142
143 const uint16_t status = pio_read_16(&registers->usbcmd);
144 if (status != 0)
145 usb_log_warning("Previous command value: %x.\n", status);
146
147 /* Start the hc with large(64B) packet FSBR */
148 pio_write_16(&registers->usbcmd,
149 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
150}
151/*----------------------------------------------------------------------------*/
152/** Initialize UHCI hc memory structures.
153 *
154 * @param[in] instance UHCI structure to use.
155 * @return Error code
156 * @note Should be called only once on any structure.
157 *
158 * Structures:
159 * - interrupt code (I/O addressses are customized per instance)
160 * - transfer lists (queue heads need to be accessible by the hw)
161 * - frame list page (needs to be one UHCI hw accessible 4K page)
162 */
163int hc_init_mem_structures(hc_t *instance)
164{
165 assert(instance);
166#define CHECK_RET_RETURN(ret, message...) \
167 if (ret != EOK) { \
168 usb_log_error(message); \
169 return ret; \
170 } else (void) 0
171
172 /* Init interrupt code */
173 instance->interrupt_code.cmds = instance->interrupt_commands;
174 {
175 /* Read status register */
176 instance->interrupt_commands[0].cmd = CMD_PIO_READ_16;
177 instance->interrupt_commands[0].dstarg = 1;
178 instance->interrupt_commands[0].addr =
179 &instance->registers->usbsts;
180
181 /* Test whether we are the interrupt cause */
182 instance->interrupt_commands[1].cmd = CMD_BTEST;
183 instance->interrupt_commands[1].value =
184 UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS;
185 instance->interrupt_commands[1].srcarg = 1;
186 instance->interrupt_commands[1].dstarg = 2;
187
188 /* Predicate cleaning and accepting */
189 instance->interrupt_commands[2].cmd = CMD_PREDICATE;
190 instance->interrupt_commands[2].value = 2;
191 instance->interrupt_commands[2].srcarg = 2;
192
193 /* Write clean status register */
194 instance->interrupt_commands[3].cmd = CMD_PIO_WRITE_A_16;
195 instance->interrupt_commands[3].srcarg = 1;
196 instance->interrupt_commands[3].addr =
197 &instance->registers->usbsts;
198
199 /* Accept interrupt */
200 instance->interrupt_commands[4].cmd = CMD_ACCEPT;
201
202 instance->interrupt_code.cmdcount = UHCI_NEEDED_IRQ_COMMANDS;
203 }
204
205 /* Init transfer lists */
206 int ret = hc_init_transfer_lists(instance);
207 CHECK_RET_RETURN(ret, "Failed to init transfer lists.\n");
208 usb_log_debug("Initialized transfer lists.\n");
209
210 /* Init USB frame list page*/
211 instance->frame_list = get_page();
212 ret = instance->frame_list ? EOK : ENOMEM;
213 CHECK_RET_RETURN(ret, "Failed to get frame list page.\n");
214 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
215
216 /* Set all frames to point to the first queue head */
217 const uint32_t queue = LINK_POINTER_QH(
218 addr_to_phys(instance->transfers_interrupt.queue_head));
219
220 unsigned i = 0;
221 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
222 instance->frame_list[i] = queue;
223 }
224
225 /* Init device keeper */
226 usb_device_keeper_init(&instance->manager);
227 usb_log_debug("Initialized device manager.\n");
228
229 ret = usb_endpoint_manager_init(&instance->ep_manager,
230 BANDWIDTH_AVAILABLE_USB11);
231 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
232 str_error(ret));
233
234 return EOK;
235#undef CHECK_RET_RETURN
236}
237/*----------------------------------------------------------------------------*/
238/** Initialize UHCI hc transfer lists.
239 *
240 * @param[in] instance UHCI structure to use.
241 * @return Error code
242 * @note Should be called only once on any structure.
243 *
244 * Initializes transfer lists and sets them in one chain to support proper
245 * USB scheduling. Sets pointer table for quick access.
246 */
247int hc_init_transfer_lists(hc_t *instance)
248{
249 assert(instance);
250#define SETUP_TRANSFER_LIST(type, name) \
251do { \
252 int ret = transfer_list_init(&instance->transfers_##type, name); \
253 if (ret != EOK) { \
254 usb_log_error("Failed(%d) to setup %s transfer list: %s.\n", \
255 ret, name, str_error(ret)); \
256 transfer_list_fini(&instance->transfers_bulk_full); \
257 transfer_list_fini(&instance->transfers_control_full); \
258 transfer_list_fini(&instance->transfers_control_slow); \
259 transfer_list_fini(&instance->transfers_interrupt); \
260 return ret; \
261 } \
262} while (0)
263
264 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
265 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
266 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
267 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
268#undef SETUP_TRANSFER_LIST
269 /* Connect lists into one schedule */
270 transfer_list_set_next(&instance->transfers_control_full,
271 &instance->transfers_bulk_full);
272 transfer_list_set_next(&instance->transfers_control_slow,
273 &instance->transfers_control_full);
274 transfer_list_set_next(&instance->transfers_interrupt,
275 &instance->transfers_control_slow);
276
277 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
278 * buggy on certain hw, enable at your own risk. */
279#ifdef FSBR
280 transfer_list_set_next(&instance->transfers_bulk_full,
281 &instance->transfers_control_full);
282#endif
283
284 /* Assign pointers to be used during scheduling */
285 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
286 &instance->transfers_interrupt;
287 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
288 &instance->transfers_interrupt;
289 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
290 &instance->transfers_control_full;
291 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
292 &instance->transfers_control_slow;
293 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
294 &instance->transfers_bulk_full;
295
296 return EOK;
297#undef CHECK_RET_CLEAR_RETURN
298}
299/*----------------------------------------------------------------------------*/
300/** Schedule batch for execution.
301 *
302 * @param[in] instance UHCI structure to use.
303 * @param[in] batch Transfer batch to schedule.
304 * @return Error code
305 *
306 * Checks for bandwidth availability and appends the batch to the proper queue.
307 */
308int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
309{
310 assert(instance);
311 assert(batch);
312
313 transfer_list_t *list =
314 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
315 assert(list);
316 transfer_list_add_batch(list, batch);
317
318 return EOK;
319}
320/*----------------------------------------------------------------------------*/
321/** Take action based on the interrupt cause.
322 *
323 * @param[in] instance UHCI structure to use.
324 * @param[in] status Value of the status register at the time of interrupt.
325 *
326 * Interrupt might indicate:
327 * - transaction completed, either by triggering IOC, SPD, or an error
328 * - some kind of device error
329 * - resume from suspend state (not implemented)
330 */
331void hc_interrupt(hc_t *instance, uint16_t status)
332{
333 assert(instance);
334 /* Lower 2 bits are transaction error and transaction complete */
335 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
336 LIST_INITIALIZE(done);
337 transfer_list_remove_finished(
338 &instance->transfers_interrupt, &done);
339 transfer_list_remove_finished(
340 &instance->transfers_control_slow, &done);
341 transfer_list_remove_finished(
342 &instance->transfers_control_full, &done);
343 transfer_list_remove_finished(
344 &instance->transfers_bulk_full, &done);
345
346 while (!list_empty(&done)) {
347 link_t *item = done.next;
348 list_remove(item);
349 usb_transfer_batch_t *batch =
350 list_get_instance(item, usb_transfer_batch_t, link);
351 usb_transfer_batch_finish(batch);
352 }
353 }
354 /* Resume interrupts are not supported */
355 if (status & UHCI_STATUS_RESUME) {
356 usb_log_error("Resume interrupt!\n");
357 }
358
359 /* Bits 4 and 5 indicate hc error */
360 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
361 usb_log_error("UHCI hardware failure!.\n");
362 ++instance->hw_failures;
363 transfer_list_abort_all(&instance->transfers_interrupt);
364 transfer_list_abort_all(&instance->transfers_control_slow);
365 transfer_list_abort_all(&instance->transfers_control_full);
366 transfer_list_abort_all(&instance->transfers_bulk_full);
367
368 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
369 /* reinitialize hw, this triggers virtual disconnect*/
370 hc_init_hw(instance);
371 } else {
372 usb_log_fatal("Too many UHCI hardware failures!.\n");
373 hc_fini(instance);
374 }
375 }
376}
377/*----------------------------------------------------------------------------*/
378/** Polling function, emulates interrupts.
379 *
380 * @param[in] arg UHCI hc structure to use.
381 * @return EOK (should never return)
382 */
383int hc_interrupt_emulator(void* arg)
384{
385 usb_log_debug("Started interrupt emulator.\n");
386 hc_t *instance = arg;
387 assert(instance);
388
389 while (1) {
390 /* Read and clear status register */
391 uint16_t status = pio_read_16(&instance->registers->usbsts);
392 pio_write_16(&instance->registers->usbsts, status);
393 if (status != 0)
394 usb_log_debug2("UHCI status: %x.\n", status);
395// Qemu fails to report stalled communication
396// see https://bugs.launchpad.net/qemu/+bug/757654
397// This is a simple workaround to force queue processing every time
398 // status |= 1;
399 hc_interrupt(instance, status);
400 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
401 }
402 return EOK;
403}
404/*---------------------------------------------------------------------------*/
405/** Debug function, checks consistency of memory structures.
406 *
407 * @param[in] arg UHCI structure to use.
408 * @return EOK (should never return)
409 */
410int hc_debug_checker(void *arg)
411{
412 hc_t *instance = arg;
413 assert(instance);
414
415#define QH(queue) \
416 instance->transfers_##queue.queue_head
417
418 while (1) {
419 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
420 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
421 const uint16_t intr =
422 pio_read_16(&instance->registers->usbintr);
423
424 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
425 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
426 cmd, sts, intr);
427 }
428
429 const uintptr_t frame_list =
430 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
431 if (frame_list != addr_to_phys(instance->frame_list)) {
432 usb_log_debug("Framelist address: %p vs. %p.\n",
433 (void *) frame_list,
434 (void *) addr_to_phys(instance->frame_list));
435 }
436
437 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
438
439 uintptr_t expected_pa = instance->frame_list[frnum]
440 & LINK_POINTER_ADDRESS_MASK;
441 uintptr_t real_pa = addr_to_phys(QH(interrupt));
442 if (expected_pa != real_pa) {
443 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
444 (void *) expected_pa, frnum, (void *) real_pa);
445 }
446
447 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
448 real_pa = addr_to_phys(QH(control_slow));
449 if (expected_pa != real_pa) {
450 usb_log_debug("Control Slow QH: %p vs. %p.\n",
451 (void *) expected_pa, (void *) real_pa);
452 }
453
454 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
455 real_pa = addr_to_phys(QH(control_full));
456 if (expected_pa != real_pa) {
457 usb_log_debug("Control Full QH: %p vs. %p.\n",
458 (void *) expected_pa, (void *) real_pa);
459 }
460
461 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
462 real_pa = addr_to_phys(QH(bulk_full));
463 if (expected_pa != real_pa ) {
464 usb_log_debug("Bulk QH: %p vs. %p.\n",
465 (void *) expected_pa, (void *) real_pa);
466 }
467 async_usleep(UHCI_DEBUGER_TIMEOUT);
468 }
469 return EOK;
470#undef QH
471}
472/**
473 * @}
474 */
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