source: mainline/uspace/drv/uhci-hcd/hc.c@ df40775

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since df40775 was 65369473, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int hc_init_transfer_lists(hc_t *instance);
63static int hc_init_mem_structures(hc_t *instance);
64static void hc_init_hw(hc_t *instance);
65
66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
68
69static bool usb_is_allowed(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
72/** Initialize UHCI hcd driver structure
73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
83 */
84int hc_init(hc_t *instance, ddf_fun_t *fun,
85 void *regs, size_t reg_size, bool interrupts)
86{
87 assert(reg_size >= sizeof(regs_t));
88 int ret;
89
90#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
91 if (ret != EOK) { \
92 usb_log_error(message); \
93 if (instance->ddf_instance) \
94 ddf_fun_destroy(instance->ddf_instance); \
95 return ret; \
96 } else (void) 0
97
98 instance->hw_interrupts = interrupts;
99 instance->hw_failures = 0;
100
101 /* Setup UHCI function. */
102 instance->ddf_instance = fun;
103
104 /* allow access to hc control registers */
105 regs_t *io;
106 ret = pio_enable(regs, reg_size, (void**)&io);
107 CHECK_RET_DEST_FUN_RETURN(ret,
108 "Failed(%d) to gain access to registers at %p: %s.\n",
109 ret, str_error(ret), io);
110 instance->registers = io;
111 usb_log_debug("Device registers at %p(%u) accessible.\n",
112 io, reg_size);
113
114 ret = hc_init_mem_structures(instance);
115 CHECK_RET_DEST_FUN_RETURN(ret,
116 "Failed to initialize UHCI memory structures.\n");
117
118 hc_init_hw(instance);
119 if (!interrupts) {
120 instance->cleaner =
121 fibril_create(hc_interrupt_emulator, instance);
122 fibril_add_ready(instance->cleaner);
123 } else {
124 /* TODO: enable interrupts here */
125 }
126
127 instance->debug_checker =
128 fibril_create(hc_debug_checker, instance);
129// fibril_add_ready(instance->debug_checker);
130
131 return EOK;
132#undef CHECK_RET_DEST_FUN_RETURN
133}
134/*----------------------------------------------------------------------------*/
135/** Initialize UHCI hc hw resources.
136 *
137 * @param[in] instance UHCI structure to use.
138 * For magic values see UHCI Design Guide
139 */
140void hc_init_hw(hc_t *instance)
141{
142 assert(instance);
143 regs_t *registers = instance->registers;
144
145 /* Reset everything, who knows what touched it before us */
146 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
147 async_usleep(10000); /* 10ms according to USB spec */
148 pio_write_16(&registers->usbcmd, 0);
149
150 /* Reset hc, all states and counters */
151 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
152 do { async_usleep(10); }
153 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
154
155 /* Set frame to exactly 1ms */
156 pio_write_8(&registers->sofmod, 64);
157
158 /* Set frame list pointer */
159 const uint32_t pa = addr_to_phys(instance->frame_list);
160 pio_write_32(&registers->flbaseadd, pa);
161
162 if (instance->hw_interrupts) {
163 /* Enable all interrupts, but resume interrupt */
164 pio_write_16(&instance->registers->usbintr,
165 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
166 }
167
168 uint16_t status = pio_read_16(&registers->usbcmd);
169 if (status != 0)
170 usb_log_warning("Previous command value: %x.\n", status);
171
172 /* Start the hc with large(64B) packet FSBR */
173 pio_write_16(&registers->usbcmd,
174 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
175}
176/*----------------------------------------------------------------------------*/
177/** Initialize UHCI hc memory structures.
178 *
179 * @param[in] instance UHCI structure to use.
180 * @return Error code
181 * @note Should be called only once on any structure.
182 *
183 * Structures:
184 * - interrupt code (I/O addressses are customized per instance)
185 * - transfer lists (queue heads need to be accessible by the hw)
186 * - frame list page (needs to be one UHCI hw accessible 4K page)
187 */
188int hc_init_mem_structures(hc_t *instance)
189{
190 assert(instance);
191#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
192 if (ret != EOK) { \
193 usb_log_error(message); \
194 if (instance->interrupt_code.cmds != NULL) \
195 free(instance->interrupt_code.cmds); \
196 return ret; \
197 } else (void) 0
198
199 /* Init interrupt code */
200 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
201 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
202 CHECK_RET_DEST_CMDS_RETURN(ret,
203 "Failed to allocate interrupt cmds space.\n");
204
205 {
206 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
207 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
208 interrupt_commands[0].addr =
209 (void*)&instance->registers->usbsts;
210 interrupt_commands[1].addr =
211 (void*)&instance->registers->usbsts;
212 instance->interrupt_code.cmdcount =
213 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
214 }
215
216 /* Init transfer lists */
217 ret = hc_init_transfer_lists(instance);
218 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
219 usb_log_debug("Initialized transfer lists.\n");
220
221 /* Init USB frame list page*/
222 instance->frame_list = get_page();
223 ret = instance ? EOK : ENOMEM;
224 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
225 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
226
227 /* Set all frames to point to the first queue head */
228 const uint32_t queue =
229 instance->transfers_interrupt.queue_head_pa
230 | LINK_POINTER_QUEUE_HEAD_FLAG;
231
232 unsigned i = 0;
233 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
234 instance->frame_list[i] = queue;
235 }
236
237 /* Init device keeper*/
238 usb_device_keeper_init(&instance->manager);
239 usb_log_debug("Initialized device manager.\n");
240
241 ret = bandwidth_init(&instance->bandwidth, BANDWIDTH_AVAILABLE_USB11,
242 bandwidth_count_usb11);
243 assert(ret == EOK);
244
245 return EOK;
246#undef CHECK_RET_DEST_CMDS_RETURN
247}
248/*----------------------------------------------------------------------------*/
249/** Initialize UHCI hc transfer lists.
250 *
251 * @param[in] instance UHCI structure to use.
252 * @return Error code
253 * @note Should be called only once on any structure.
254 *
255 * Initializes transfer lists and sets them in one chain to support proper
256 * USB scheduling. Sets pointer table for quick access.
257 */
258int hc_init_transfer_lists(hc_t *instance)
259{
260 assert(instance);
261#define CHECK_RET_CLEAR_RETURN(ret, message...) \
262 if (ret != EOK) { \
263 usb_log_error(message); \
264 transfer_list_fini(&instance->transfers_bulk_full); \
265 transfer_list_fini(&instance->transfers_control_full); \
266 transfer_list_fini(&instance->transfers_control_slow); \
267 transfer_list_fini(&instance->transfers_interrupt); \
268 return ret; \
269 } else (void) 0
270
271 /* initialize TODO: check errors */
272 int ret;
273 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
274 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
275
276 ret = transfer_list_init(
277 &instance->transfers_control_full, "CONTROL_FULL");
278 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
279
280 ret = transfer_list_init(
281 &instance->transfers_control_slow, "CONTROL_SLOW");
282 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
283
284 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
285 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
286
287 transfer_list_set_next(&instance->transfers_control_full,
288 &instance->transfers_bulk_full);
289 transfer_list_set_next(&instance->transfers_control_slow,
290 &instance->transfers_control_full);
291 transfer_list_set_next(&instance->transfers_interrupt,
292 &instance->transfers_control_slow);
293
294 /*FSBR*/
295#ifdef FSBR
296 transfer_list_set_next(&instance->transfers_bulk_full,
297 &instance->transfers_control_full);
298#endif
299
300 /* Assign pointers to be used during scheduling */
301 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
302 &instance->transfers_interrupt;
303 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
304 &instance->transfers_interrupt;
305 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
306 &instance->transfers_control_full;
307 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
308 &instance->transfers_control_slow;
309 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
310 &instance->transfers_bulk_full;
311
312 return EOK;
313#undef CHECK_RET_CLEAR_RETURN
314}
315/*----------------------------------------------------------------------------*/
316/** Schedule batch for execution.
317 *
318 * @param[in] instance UHCI structure to use.
319 * @param[in] batch Transfer batch to schedule.
320 * @return Error code
321 *
322 * Checks for bandwidth availability and appends the batch to the proper queue.
323 */
324int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
325{
326 assert(instance);
327 assert(batch);
328 const int low_speed = (batch->speed == USB_SPEED_LOW);
329 if (!usb_is_allowed(
330 low_speed, batch->transfer_type, batch->max_packet_size)) {
331 usb_log_error("Invalid USB transfer specified %s %d %zu.\n",
332 usb_str_speed(batch->speed), batch->transfer_type,
333 batch->max_packet_size);
334 return ENOTSUP;
335 }
336 /* Check available bandwidth */
337 if (batch->transfer_type == USB_TRANSFER_INTERRUPT ||
338 batch->transfer_type == USB_TRANSFER_ISOCHRONOUS) {
339 size_t bw = bandwidth_count_usb11(batch->speed,
340 batch->transfer_type, batch->buffer_size,
341 batch->max_packet_size);
342 int ret =
343 bandwidth_use(&instance->bandwidth, batch->target.address,
344 batch->target.endpoint, batch->direction, bw);
345 if (ret != EOK) {
346 usb_log_warning("Failed(%d) to use reserved bw: %s.\n",
347 ret, str_error(ret));
348 }
349 }
350
351 transfer_list_t *list =
352 instance->transfers[batch->speed][batch->transfer_type];
353 assert(list);
354 if (batch->transfer_type == USB_TRANSFER_CONTROL) {
355 usb_device_keeper_use_control(
356 &instance->manager, batch->target);
357 }
358 transfer_list_add_batch(list, batch);
359
360 return EOK;
361}
362/*----------------------------------------------------------------------------*/
363/** Take action based on the interrupt cause.
364 *
365 * @param[in] instance UHCI structure to use.
366 * @param[in] status Value of the status register at the time of interrupt.
367 *
368 * Interrupt might indicate:
369 * - transaction completed, either by triggering IOC, SPD, or an error
370 * - some kind of device error
371 * - resume from suspend state (not implemented)
372 */
373void hc_interrupt(hc_t *instance, uint16_t status)
374{
375 assert(instance);
376// status |= 1; //Uncomment to work around qemu hang
377 /* TODO: Resume interrupts are not supported */
378 /* Lower 2 bits are transaction error and transaction complete */
379 if (status & 0x3) {
380 LIST_INITIALIZE(done);
381 transfer_list_remove_finished(
382 &instance->transfers_interrupt, &done);
383 transfer_list_remove_finished(
384 &instance->transfers_control_slow, &done);
385 transfer_list_remove_finished(
386 &instance->transfers_control_full, &done);
387 transfer_list_remove_finished(
388 &instance->transfers_bulk_full, &done);
389
390 while (!list_empty(&done)) {
391 link_t *item = done.next;
392 list_remove(item);
393 usb_transfer_batch_t *batch =
394 list_get_instance(item, usb_transfer_batch_t, link);
395 switch (batch->transfer_type)
396 {
397 case USB_TRANSFER_CONTROL:
398 usb_device_keeper_release_control(
399 &instance->manager, batch->target);
400 break;
401 case USB_TRANSFER_INTERRUPT:
402 case USB_TRANSFER_ISOCHRONOUS: {
403 int ret = bandwidth_free(&instance->bandwidth,
404 batch->target.address,
405 batch->target.endpoint,
406 batch->direction);
407 if (ret != EOK)
408 usb_log_warning("Failed(%d) to free "
409 "reserved bw: %s.\n", ret,
410 str_error(ret));
411 }
412 default:
413 break;
414 }
415 batch->next_step(batch);
416 }
417 }
418 /* bits 4 and 5 indicate hc error */
419 if (status & 0x18) {
420 usb_log_error("UHCI hardware failure!.\n");
421 ++instance->hw_failures;
422 transfer_list_abort_all(&instance->transfers_interrupt);
423 transfer_list_abort_all(&instance->transfers_control_slow);
424 transfer_list_abort_all(&instance->transfers_control_full);
425 transfer_list_abort_all(&instance->transfers_bulk_full);
426
427 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
428 /* reinitialize hw, this triggers virtual disconnect*/
429 hc_init_hw(instance);
430 } else {
431 usb_log_fatal("Too many UHCI hardware failures!.\n");
432 hc_fini(instance);
433 }
434 }
435}
436/*----------------------------------------------------------------------------*/
437/** Polling function, emulates interrupts.
438 *
439 * @param[in] arg UHCI hc structure to use.
440 * @return EOK (should never return)
441 */
442int hc_interrupt_emulator(void* arg)
443{
444 usb_log_debug("Started interrupt emulator.\n");
445 hc_t *instance = (hc_t*)arg;
446 assert(instance);
447
448 while (1) {
449 /* read and ack interrupts */
450 uint16_t status = pio_read_16(&instance->registers->usbsts);
451 pio_write_16(&instance->registers->usbsts, 0x1f);
452 if (status != 0)
453 usb_log_debug2("UHCI status: %x.\n", status);
454 hc_interrupt(instance, status);
455 async_usleep(UHCI_CLEANER_TIMEOUT);
456 }
457 return EOK;
458}
459/*---------------------------------------------------------------------------*/
460/** Debug function, checks consistency of memory structures.
461 *
462 * @param[in] arg UHCI structure to use.
463 * @return EOK (should never return)
464 */
465int hc_debug_checker(void *arg)
466{
467 hc_t *instance = (hc_t*)arg;
468 assert(instance);
469
470#define QH(queue) \
471 instance->transfers_##queue.queue_head
472
473 while (1) {
474 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
475 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
476 const uint16_t intr =
477 pio_read_16(&instance->registers->usbintr);
478
479 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
480 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
481 cmd, sts, intr);
482 }
483
484 uintptr_t frame_list =
485 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
486 if (frame_list != addr_to_phys(instance->frame_list)) {
487 usb_log_debug("Framelist address: %p vs. %p.\n",
488 frame_list, addr_to_phys(instance->frame_list));
489 }
490
491 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
492
493 uintptr_t expected_pa = instance->frame_list[frnum]
494 & LINK_POINTER_ADDRESS_MASK;
495 uintptr_t real_pa = addr_to_phys(QH(interrupt));
496 if (expected_pa != real_pa) {
497 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
498 expected_pa, frnum, real_pa);
499 }
500
501 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
502 real_pa = addr_to_phys(QH(control_slow));
503 if (expected_pa != real_pa) {
504 usb_log_debug("Control Slow QH: %p vs. %p.\n",
505 expected_pa, real_pa);
506 }
507
508 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
509 real_pa = addr_to_phys(QH(control_full));
510 if (expected_pa != real_pa) {
511 usb_log_debug("Control Full QH: %p vs. %p.\n",
512 expected_pa, real_pa);
513 }
514
515 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
516 real_pa = addr_to_phys(QH(bulk_full));
517 if (expected_pa != real_pa ) {
518 usb_log_debug("Bulk QH: %p vs. %p.\n",
519 expected_pa, real_pa);
520 }
521 async_usleep(UHCI_DEBUGER_TIMEOUT);
522 }
523 return EOK;
524#undef QH
525}
526/*----------------------------------------------------------------------------*/
527/** Check transfers for USB validity
528 *
529 * @param[in] low_speed Transfer speed.
530 * @param[in] transfer Transer type
531 * @param[in] size Size of data packets
532 * @return True if transaction is allowed by USB specs, false otherwise
533 */
534bool usb_is_allowed(
535 bool low_speed, usb_transfer_type_t transfer, size_t size)
536{
537 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
538 switch(transfer)
539 {
540 case USB_TRANSFER_ISOCHRONOUS:
541 return (!low_speed && size < 1024);
542 case USB_TRANSFER_INTERRUPT:
543 return size <= (low_speed ? 8 : 64);
544 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
545 return (size <= (low_speed ? 8 : 64));
546 case USB_TRANSFER_BULK: /* device specifies its own max size */
547 return (!low_speed && size <= 64);
548 }
549 return false;
550}
551/**
552 * @}
553 */
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