[9351353] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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[17ceb72] | 28 | /** @addtogroup drvusbuhcihc
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[9351353] | 29 | * @{
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| 30 | */
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| 31 | /** @file
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[17ceb72] | 32 | * @brief UHCI Host controller driver routines
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[9351353] | 33 | */
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| 34 | #include <errno.h>
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| 35 | #include <str_error.h>
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| 36 | #include <adt/list.h>
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| 37 | #include <libarch/ddi.h>
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| 38 |
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| 39 | #include <usb/debug.h>
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| 40 | #include <usb/usb.h>
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| 41 | #include <usb/ddfiface.h>
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| 42 | #include <usb_iface.h>
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| 43 |
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[c01cd32] | 44 | #include "hc.h"
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[9351353] | 45 |
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[8986412] | 46 | #define UHCI_INTR_ALLOW_INTERRUPTS \
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[af81980] | 47 | (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
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[8986412] | 48 | #define UHCI_STATUS_USED_INTERRUPTS \
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| 49 | (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
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[af81980] | 50 |
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[302a4b6] | 51 |
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[c01cd32] | 52 | static int hc_init_transfer_lists(hc_t *instance);
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| 53 | static int hc_init_mem_structures(hc_t *instance);
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| 54 | static void hc_init_hw(hc_t *instance);
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[9351353] | 55 |
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[c01cd32] | 56 | static int hc_interrupt_emulator(void *arg);
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| 57 | static int hc_debug_checker(void *arg);
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[9351353] | 58 | /*----------------------------------------------------------------------------*/
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[02cacce] | 59 | /** Initialize UHCI hc driver structure
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[9351353] | 60 | *
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| 61 | * @param[in] instance Memory place to initialize.
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| 62 | * @param[in] regs Address of I/O control registers.
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[23f40280] | 63 | * @param[in] reg_size Size of I/O control registers.
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| 64 | * @param[in] interrupts True if hw interrupts should be used.
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[9351353] | 65 | * @return Error code.
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| 66 | * @note Should be called only once on any structure.
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[17ceb72] | 67 | *
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| 68 | * Initializes memory structures, starts up hw, and launches debugger and
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| 69 | * interrupt fibrils.
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[9351353] | 70 | */
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[d2bff2f] | 71 | int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
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[9351353] | 72 | {
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| 73 | assert(reg_size >= sizeof(regs_t));
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| 74 | int ret;
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| 75 |
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[ea993d18] | 76 | #define CHECK_RET_RETURN(ret, message...) \
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[9351353] | 77 | if (ret != EOK) { \
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| 78 | usb_log_error(message); \
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| 79 | return ret; \
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| 80 | } else (void) 0
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| 81 |
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[ff34e5a] | 82 | instance->hw_interrupts = interrupts;
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[fcc525d] | 83 | instance->hw_failures = 0;
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| 84 |
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[9351353] | 85 | /* allow access to hc control registers */
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| 86 | regs_t *io;
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[e247d83] | 87 | ret = pio_enable(regs, reg_size, (void **)&io);
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[ea993d18] | 88 | CHECK_RET_RETURN(ret,
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[9351353] | 89 | "Failed(%d) to gain access to registers at %p: %s.\n",
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[ea993d18] | 90 | ret, io, str_error(ret));
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[9351353] | 91 | instance->registers = io;
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[4125b7d] | 92 | usb_log_debug("Device registers at %p (%zuB) accessible.\n",
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[9351353] | 93 | io, reg_size);
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| 94 |
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[c01cd32] | 95 | ret = hc_init_mem_structures(instance);
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[ea993d18] | 96 | CHECK_RET_RETURN(ret,
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| 97 | "Failed(%d) to initialize UHCI memory structures: %s.\n",
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| 98 | ret, str_error(ret));
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[9351353] | 99 |
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[c01cd32] | 100 | hc_init_hw(instance);
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[ff34e5a] | 101 | if (!interrupts) {
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[ea993d18] | 102 | instance->interrupt_emulator =
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[c01cd32] | 103 | fibril_create(hc_interrupt_emulator, instance);
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[ea993d18] | 104 | fibril_add_ready(instance->interrupt_emulator);
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[ff34e5a] | 105 | }
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[ea993d18] | 106 | (void)hc_debug_checker;
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[9351353] | 107 |
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| 108 | return EOK;
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| 109 | #undef CHECK_RET_DEST_FUN_RETURN
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| 110 | }
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| 111 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 112 | /** Initialize UHCI hc hw resources.
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[9351353] | 113 | *
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| 114 | * @param[in] instance UHCI structure to use.
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[17ceb72] | 115 | * For magic values see UHCI Design Guide
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[9351353] | 116 | */
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[c01cd32] | 117 | void hc_init_hw(hc_t *instance)
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[9351353] | 118 | {
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| 119 | assert(instance);
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| 120 | regs_t *registers = instance->registers;
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| 121 |
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| 122 | /* Reset everything, who knows what touched it before us */
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| 123 | pio_write_16(®isters->usbcmd, UHCI_CMD_GLOBAL_RESET);
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| 124 | async_usleep(10000); /* 10ms according to USB spec */
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| 125 | pio_write_16(®isters->usbcmd, 0);
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| 126 |
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| 127 | /* Reset hc, all states and counters */
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| 128 | pio_write_16(®isters->usbcmd, UHCI_CMD_HCRESET);
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| 129 | do { async_usleep(10); }
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| 130 | while ((pio_read_16(®isters->usbcmd) & UHCI_CMD_HCRESET) != 0);
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| 131 |
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[eb2a48a] | 132 | /* Set frame to exactly 1ms */
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| 133 | pio_write_8(®isters->sofmod, 64);
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| 134 |
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| 135 | /* Set frame list pointer */
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[9351353] | 136 | const uint32_t pa = addr_to_phys(instance->frame_list);
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| 137 | pio_write_32(®isters->flbaseadd, pa);
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| 138 |
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[ff34e5a] | 139 | if (instance->hw_interrupts) {
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| 140 | /* Enable all interrupts, but resume interrupt */
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| 141 | pio_write_16(&instance->registers->usbintr,
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[8986412] | 142 | UHCI_INTR_ALLOW_INTERRUPTS);
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[ff34e5a] | 143 | }
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[9351353] | 144 |
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[e247d83] | 145 | const uint16_t status = pio_read_16(®isters->usbcmd);
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[9351353] | 146 | if (status != 0)
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| 147 | usb_log_warning("Previous command value: %x.\n", status);
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| 148 |
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| 149 | /* Start the hc with large(64B) packet FSBR */
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| 150 | pio_write_16(®isters->usbcmd,
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| 151 | UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
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| 152 | }
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| 153 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 154 | /** Initialize UHCI hc memory structures.
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[9351353] | 155 | *
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| 156 | * @param[in] instance UHCI structure to use.
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| 157 | * @return Error code
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| 158 | * @note Should be called only once on any structure.
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[17ceb72] | 159 | *
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| 160 | * Structures:
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| 161 | * - interrupt code (I/O addressses are customized per instance)
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| 162 | * - transfer lists (queue heads need to be accessible by the hw)
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| 163 | * - frame list page (needs to be one UHCI hw accessible 4K page)
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[9351353] | 164 | */
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[c01cd32] | 165 | int hc_init_mem_structures(hc_t *instance)
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[9351353] | 166 | {
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| 167 | assert(instance);
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[77d10f0] | 168 | #define CHECK_RET_RETURN(ret, message...) \
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[9351353] | 169 | if (ret != EOK) { \
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| 170 | usb_log_error(message); \
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| 171 | return ret; \
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| 172 | } else (void) 0
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| 173 |
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| 174 | /* Init interrupt code */
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[77d10f0] | 175 | instance->interrupt_code.cmds = instance->interrupt_commands;
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[9351353] | 176 | {
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[af81980] | 177 | /* Read status register */
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[77d10f0] | 178 | instance->interrupt_commands[0].cmd = CMD_PIO_READ_16;
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| 179 | instance->interrupt_commands[0].dstarg = 1;
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| 180 | instance->interrupt_commands[0].addr =
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| 181 | &instance->registers->usbsts;
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| 182 |
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[af81980] | 183 | /* Test whether we are the interrupt cause */
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| 184 | instance->interrupt_commands[1].cmd = CMD_BTEST;
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| 185 | instance->interrupt_commands[1].value =
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[8986412] | 186 | UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS;
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[af81980] | 187 | instance->interrupt_commands[1].srcarg = 1;
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| 188 | instance->interrupt_commands[1].dstarg = 2;
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| 189 |
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| 190 | /* Predicate cleaning and accepting */
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| 191 | instance->interrupt_commands[2].cmd = CMD_PREDICATE;
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| 192 | instance->interrupt_commands[2].value = 2;
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| 193 | instance->interrupt_commands[2].srcarg = 2;
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| 194 |
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| 195 | /* Write clean status register */
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| 196 | instance->interrupt_commands[3].cmd = CMD_PIO_WRITE_A_16;
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| 197 | instance->interrupt_commands[3].srcarg = 1;
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| 198 | instance->interrupt_commands[3].addr =
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[77d10f0] | 199 | &instance->registers->usbsts;
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| 200 |
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[af81980] | 201 | /* Accept interrupt */
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| 202 | instance->interrupt_commands[4].cmd = CMD_ACCEPT;
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| 203 |
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[77d10f0] | 204 | instance->interrupt_code.cmdcount = UHCI_NEEDED_IRQ_COMMANDS;
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[9351353] | 205 | }
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| 206 |
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| 207 | /* Init transfer lists */
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[77d10f0] | 208 | int ret = hc_init_transfer_lists(instance);
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| 209 | CHECK_RET_RETURN(ret, "Failed to init transfer lists.\n");
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[9351353] | 210 | usb_log_debug("Initialized transfer lists.\n");
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| 211 |
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| 212 | /* Init USB frame list page*/
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| 213 | instance->frame_list = get_page();
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[e247d83] | 214 | ret = instance->frame_list ? EOK : ENOMEM;
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[77d10f0] | 215 | CHECK_RET_RETURN(ret, "Failed to get frame list page.\n");
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[001b152] | 216 | usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
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[9351353] | 217 |
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| 218 | /* Set all frames to point to the first queue head */
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[302a4b6] | 219 | const uint32_t queue = LINK_POINTER_QH(
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| 220 | addr_to_phys(instance->transfers_interrupt.queue_head));
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[9351353] | 221 |
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| 222 | unsigned i = 0;
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| 223 | for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
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| 224 | instance->frame_list[i] = queue;
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| 225 | }
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| 226 |
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[4c70554] | 227 | /* Init device keeper */
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[62ed5bc] | 228 | usb_device_keeper_init(&instance->manager);
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[9351353] | 229 | usb_log_debug("Initialized device manager.\n");
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| 230 |
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[4c28d17] | 231 | ret = usb_endpoint_manager_init(&instance->ep_manager,
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| 232 | BANDWIDTH_AVAILABLE_USB11);
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[77d10f0] | 233 | CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
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| 234 | str_error(ret));
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[a1313b8c] | 235 |
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[9351353] | 236 | return EOK;
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[77d10f0] | 237 | #undef CHECK_RET_RETURN
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[9351353] | 238 | }
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| 239 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 240 | /** Initialize UHCI hc transfer lists.
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[9351353] | 241 | *
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| 242 | * @param[in] instance UHCI structure to use.
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| 243 | * @return Error code
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| 244 | * @note Should be called only once on any structure.
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[17ceb72] | 245 | *
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| 246 | * Initializes transfer lists and sets them in one chain to support proper
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| 247 | * USB scheduling. Sets pointer table for quick access.
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[9351353] | 248 | */
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[c01cd32] | 249 | int hc_init_transfer_lists(hc_t *instance)
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[9351353] | 250 | {
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| 251 | assert(instance);
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[27205841] | 252 | #define SETUP_TRANSFER_LIST(type, name) \
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| 253 | do { \
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| 254 | int ret = transfer_list_init(&instance->transfers_##type, name); \
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[9351353] | 255 | if (ret != EOK) { \
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[27205841] | 256 | usb_log_error("Failed(%d) to setup %s transfer list: %s.\n", \
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| 257 | ret, name, str_error(ret)); \
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[9351353] | 258 | transfer_list_fini(&instance->transfers_bulk_full); \
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| 259 | transfer_list_fini(&instance->transfers_control_full); \
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| 260 | transfer_list_fini(&instance->transfers_control_slow); \
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| 261 | transfer_list_fini(&instance->transfers_interrupt); \
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| 262 | return ret; \
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[27205841] | 263 | } \
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| 264 | } while (0)
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| 265 |
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| 266 | SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
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| 267 | SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
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| 268 | SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
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| 269 | SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
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| 270 | #undef SETUP_TRANSFER_LIST
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| 271 | /* Connect lists into one schedule */
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[9351353] | 272 | transfer_list_set_next(&instance->transfers_control_full,
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| 273 | &instance->transfers_bulk_full);
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| 274 | transfer_list_set_next(&instance->transfers_control_slow,
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| 275 | &instance->transfers_control_full);
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| 276 | transfer_list_set_next(&instance->transfers_interrupt,
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| 277 | &instance->transfers_control_slow);
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| 278 |
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[e247d83] | 279 | /*FSBR, This feature is not needed (adds no benefit) and is supposedly
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| 280 | * buggy on certain hw, enable at your own risk. */
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[9351353] | 281 | #ifdef FSBR
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| 282 | transfer_list_set_next(&instance->transfers_bulk_full,
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[302a4b6] | 283 | &instance->transfers_control_full);
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[9351353] | 284 | #endif
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| 285 |
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| 286 | /* Assign pointers to be used during scheduling */
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| 287 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
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| 288 | &instance->transfers_interrupt;
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| 289 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
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| 290 | &instance->transfers_interrupt;
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| 291 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
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| 292 | &instance->transfers_control_full;
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| 293 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
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| 294 | &instance->transfers_control_slow;
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| 295 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
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| 296 | &instance->transfers_bulk_full;
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| 297 |
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| 298 | return EOK;
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| 299 | #undef CHECK_RET_CLEAR_RETURN
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| 300 | }
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| 301 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 302 | /** Schedule batch for execution.
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[9351353] | 303 | *
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| 304 | * @param[in] instance UHCI structure to use.
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| 305 | * @param[in] batch Transfer batch to schedule.
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| 306 | * @return Error code
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[17ceb72] | 307 | *
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| 308 | * Checks for bandwidth availability and appends the batch to the proper queue.
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[9351353] | 309 | */
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[c01cd32] | 310 | int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
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[9351353] | 311 | {
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| 312 | assert(instance);
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| 313 | assert(batch);
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| 314 |
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| 315 | transfer_list_t *list =
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[d017cea] | 316 | instance->transfers[batch->ep->speed][batch->ep->transfer_type];
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[9351353] | 317 | assert(list);
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| 318 | transfer_list_add_batch(list, batch);
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| 319 |
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| 320 | return EOK;
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| 321 | }
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| 322 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 323 | /** Take action based on the interrupt cause.
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[9351353] | 324 | *
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| 325 | * @param[in] instance UHCI structure to use.
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[17ceb72] | 326 | * @param[in] status Value of the status register at the time of interrupt.
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| 327 | *
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| 328 | * Interrupt might indicate:
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| 329 | * - transaction completed, either by triggering IOC, SPD, or an error
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| 330 | * - some kind of device error
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| 331 | * - resume from suspend state (not implemented)
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[9351353] | 332 | */
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[c01cd32] | 333 | void hc_interrupt(hc_t *instance, uint16_t status)
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[9351353] | 334 | {
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| 335 | assert(instance);
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| 336 | /* Lower 2 bits are transaction error and transaction complete */
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[27205841] | 337 | if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
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[1585c7e] | 338 | LIST_INITIALIZE(done);
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| 339 | transfer_list_remove_finished(
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| 340 | &instance->transfers_interrupt, &done);
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| 341 | transfer_list_remove_finished(
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| 342 | &instance->transfers_control_slow, &done);
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| 343 | transfer_list_remove_finished(
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| 344 | &instance->transfers_control_full, &done);
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| 345 | transfer_list_remove_finished(
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| 346 | &instance->transfers_bulk_full, &done);
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| 347 |
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| 348 | while (!list_empty(&done)) {
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| 349 | link_t *item = done.next;
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| 350 | list_remove(item);
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| 351 | usb_transfer_batch_t *batch =
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| 352 | list_get_instance(item, usb_transfer_batch_t, link);
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[cd1cec3b] | 353 | usb_transfer_batch_finish(batch);
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[1585c7e] | 354 | }
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[9351353] | 355 | }
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[27205841] | 356 | /* Resume interrupts are not supported */
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[302a4b6] | 357 | if (status & UHCI_STATUS_RESUME) {
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| 358 | usb_log_error("Resume interrupt!\n");
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| 359 | }
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[27205841] | 360 |
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| 361 | /* Bits 4 and 5 indicate hc error */
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| 362 | if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
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[fcc525d] | 363 | usb_log_error("UHCI hardware failure!.\n");
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| 364 | ++instance->hw_failures;
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[a963a68] | 365 | transfer_list_abort_all(&instance->transfers_interrupt);
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| 366 | transfer_list_abort_all(&instance->transfers_control_slow);
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| 367 | transfer_list_abort_all(&instance->transfers_control_full);
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| 368 | transfer_list_abort_all(&instance->transfers_bulk_full);
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[fcc525d] | 369 |
|
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| 370 | if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
|
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| 371 | /* reinitialize hw, this triggers virtual disconnect*/
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[c01cd32] | 372 | hc_init_hw(instance);
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[fcc525d] | 373 | } else {
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| 374 | usb_log_fatal("Too many UHCI hardware failures!.\n");
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[c01cd32] | 375 | hc_fini(instance);
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[fcc525d] | 376 | }
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[a963a68] | 377 | }
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[9351353] | 378 | }
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| 379 | /*----------------------------------------------------------------------------*/
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| 380 | /** Polling function, emulates interrupts.
|
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| 381 | *
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[17ceb72] | 382 | * @param[in] arg UHCI hc structure to use.
|
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| 383 | * @return EOK (should never return)
|
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[9351353] | 384 | */
|
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[c01cd32] | 385 | int hc_interrupt_emulator(void* arg)
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[9351353] | 386 | {
|
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| 387 | usb_log_debug("Started interrupt emulator.\n");
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[6f122df] | 388 | hc_t *instance = arg;
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[9351353] | 389 | assert(instance);
|
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| 390 |
|
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| 391 | while (1) {
|
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[6f122df] | 392 | /* Read and clear status register */
|
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[9351353] | 393 | uint16_t status = pio_read_16(&instance->registers->usbsts);
|
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[27205841] | 394 | pio_write_16(&instance->registers->usbsts, status);
|
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[9351353] | 395 | if (status != 0)
|
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| 396 | usb_log_debug2("UHCI status: %x.\n", status);
|
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[6f122df] | 397 | // Qemu fails to report stalled communication
|
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| 398 | // see https://bugs.launchpad.net/qemu/+bug/757654
|
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| 399 | // This is a simple workaround to force queue processing every time
|
---|
| 400 | // status |= 1;
|
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[c01cd32] | 401 | hc_interrupt(instance, status);
|
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[27205841] | 402 | async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
|
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[9351353] | 403 | }
|
---|
| 404 | return EOK;
|
---|
| 405 | }
|
---|
| 406 | /*---------------------------------------------------------------------------*/
|
---|
| 407 | /** Debug function, checks consistency of memory structures.
|
---|
| 408 | *
|
---|
| 409 | * @param[in] arg UHCI structure to use.
|
---|
[17ceb72] | 410 | * @return EOK (should never return)
|
---|
[9351353] | 411 | */
|
---|
[c01cd32] | 412 | int hc_debug_checker(void *arg)
|
---|
[9351353] | 413 | {
|
---|
[6f122df] | 414 | hc_t *instance = arg;
|
---|
[9351353] | 415 | assert(instance);
|
---|
| 416 |
|
---|
| 417 | #define QH(queue) \
|
---|
| 418 | instance->transfers_##queue.queue_head
|
---|
| 419 |
|
---|
| 420 | while (1) {
|
---|
| 421 | const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
|
---|
| 422 | const uint16_t sts = pio_read_16(&instance->registers->usbsts);
|
---|
| 423 | const uint16_t intr =
|
---|
| 424 | pio_read_16(&instance->registers->usbintr);
|
---|
| 425 |
|
---|
| 426 | if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
|
---|
| 427 | usb_log_debug2("Command: %X Status: %X Intr: %x\n",
|
---|
| 428 | cmd, sts, intr);
|
---|
| 429 | }
|
---|
| 430 |
|
---|
[e247d83] | 431 | const uintptr_t frame_list =
|
---|
[9351353] | 432 | pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
|
---|
| 433 | if (frame_list != addr_to_phys(instance->frame_list)) {
|
---|
| 434 | usb_log_debug("Framelist address: %p vs. %p.\n",
|
---|
[4125b7d] | 435 | (void *) frame_list,
|
---|
| 436 | (void *) addr_to_phys(instance->frame_list));
|
---|
[9351353] | 437 | }
|
---|
| 438 |
|
---|
| 439 | int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
|
---|
| 440 |
|
---|
| 441 | uintptr_t expected_pa = instance->frame_list[frnum]
|
---|
| 442 | & LINK_POINTER_ADDRESS_MASK;
|
---|
| 443 | uintptr_t real_pa = addr_to_phys(QH(interrupt));
|
---|
| 444 | if (expected_pa != real_pa) {
|
---|
[4125b7d] | 445 | usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
|
---|
| 446 | (void *) expected_pa, frnum, (void *) real_pa);
|
---|
[9351353] | 447 | }
|
---|
| 448 |
|
---|
| 449 | expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 450 | real_pa = addr_to_phys(QH(control_slow));
|
---|
| 451 | if (expected_pa != real_pa) {
|
---|
| 452 | usb_log_debug("Control Slow QH: %p vs. %p.\n",
|
---|
[4125b7d] | 453 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 454 | }
|
---|
| 455 |
|
---|
| 456 | expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 457 | real_pa = addr_to_phys(QH(control_full));
|
---|
| 458 | if (expected_pa != real_pa) {
|
---|
| 459 | usb_log_debug("Control Full QH: %p vs. %p.\n",
|
---|
[4125b7d] | 460 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 461 | }
|
---|
| 462 |
|
---|
| 463 | expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 464 | real_pa = addr_to_phys(QH(bulk_full));
|
---|
| 465 | if (expected_pa != real_pa ) {
|
---|
| 466 | usb_log_debug("Bulk QH: %p vs. %p.\n",
|
---|
[4125b7d] | 467 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 468 | }
|
---|
| 469 | async_usleep(UHCI_DEBUGER_TIMEOUT);
|
---|
| 470 | }
|
---|
| 471 | return EOK;
|
---|
| 472 | #undef QH
|
---|
| 473 | }
|
---|
| 474 | /**
|
---|
| 475 | * @}
|
---|
| 476 | */
|
---|