source: mainline/uspace/drv/uhci-hcd/hc.c@ 62ed5bc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 62ed5bc was 62ed5bc, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Rename hc.device_manager ⇒ hc.manager
  • Property mode set to 100644
File size: 16.0 KB
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[9351353]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[17ceb72]28/** @addtogroup drvusbuhcihc
[9351353]29 * @{
30 */
31/** @file
[17ceb72]32 * @brief UHCI Host controller driver routines
[9351353]33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
[c01cd32]44#include "hc.h"
[9351353]45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
[c01cd32]62static int hc_init_transfer_lists(hc_t *instance);
63static int hc_init_mem_structures(hc_t *instance);
64static void hc_init_hw(hc_t *instance);
[9351353]65
[c01cd32]66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
[9351353]68
69static bool allowed_usb_packet(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
[17ceb72]72/** Initialize UHCI hcd driver structure
[9351353]73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
[17ceb72]80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
[9351353]83 */
[c01cd32]84int hc_init(hc_t *instance, ddf_fun_t *fun,
[ff34e5a]85 void *regs, size_t reg_size, bool interrupts)
[9351353]86{
87 assert(reg_size >= sizeof(regs_t));
88 int ret;
89
90#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
91 if (ret != EOK) { \
92 usb_log_error(message); \
93 if (instance->ddf_instance) \
94 ddf_fun_destroy(instance->ddf_instance); \
95 return ret; \
96 } else (void) 0
97
[ff34e5a]98 instance->hw_interrupts = interrupts;
[fcc525d]99 instance->hw_failures = 0;
100
[9351353]101 /* Setup UHCI function. */
102 instance->ddf_instance = fun;
103
104 /* allow access to hc control registers */
105 regs_t *io;
106 ret = pio_enable(regs, reg_size, (void**)&io);
107 CHECK_RET_DEST_FUN_RETURN(ret,
108 "Failed(%d) to gain access to registers at %p: %s.\n",
109 ret, str_error(ret), io);
110 instance->registers = io;
111 usb_log_debug("Device registers at %p(%u) accessible.\n",
112 io, reg_size);
113
[c01cd32]114 ret = hc_init_mem_structures(instance);
[9351353]115 CHECK_RET_DEST_FUN_RETURN(ret,
116 "Failed to initialize UHCI memory structures.\n");
117
[c01cd32]118 hc_init_hw(instance);
[ff34e5a]119 if (!interrupts) {
120 instance->cleaner =
[c01cd32]121 fibril_create(hc_interrupt_emulator, instance);
[ff34e5a]122 fibril_add_ready(instance->cleaner);
[7d6a676]123 } else {
124 /* TODO: enable interrupts here */
[ff34e5a]125 }
[9351353]126
[13b9cb5]127 instance->debug_checker =
[c01cd32]128 fibril_create(hc_debug_checker, instance);
[13b9cb5]129// fibril_add_ready(instance->debug_checker);
[9351353]130
131 return EOK;
132#undef CHECK_RET_DEST_FUN_RETURN
133}
134/*----------------------------------------------------------------------------*/
[17ceb72]135/** Initialize UHCI hc hw resources.
[9351353]136 *
137 * @param[in] instance UHCI structure to use.
[17ceb72]138 * For magic values see UHCI Design Guide
[9351353]139 */
[c01cd32]140void hc_init_hw(hc_t *instance)
[9351353]141{
142 assert(instance);
143 regs_t *registers = instance->registers;
144
145 /* Reset everything, who knows what touched it before us */
146 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
147 async_usleep(10000); /* 10ms according to USB spec */
148 pio_write_16(&registers->usbcmd, 0);
149
150 /* Reset hc, all states and counters */
151 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
152 do { async_usleep(10); }
153 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
154
[eb2a48a]155 /* Set frame to exactly 1ms */
156 pio_write_8(&registers->sofmod, 64);
157
158 /* Set frame list pointer */
[9351353]159 const uint32_t pa = addr_to_phys(instance->frame_list);
160 pio_write_32(&registers->flbaseadd, pa);
161
[ff34e5a]162 if (instance->hw_interrupts) {
163 /* Enable all interrupts, but resume interrupt */
164 pio_write_16(&instance->registers->usbintr,
165 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
166 }
[9351353]167
168 uint16_t status = pio_read_16(&registers->usbcmd);
169 if (status != 0)
170 usb_log_warning("Previous command value: %x.\n", status);
171
172 /* Start the hc with large(64B) packet FSBR */
173 pio_write_16(&registers->usbcmd,
174 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
175}
176/*----------------------------------------------------------------------------*/
[17ceb72]177/** Initialize UHCI hc memory structures.
[9351353]178 *
179 * @param[in] instance UHCI structure to use.
180 * @return Error code
181 * @note Should be called only once on any structure.
[17ceb72]182 *
183 * Structures:
184 * - interrupt code (I/O addressses are customized per instance)
185 * - transfer lists (queue heads need to be accessible by the hw)
186 * - frame list page (needs to be one UHCI hw accessible 4K page)
[9351353]187 */
[c01cd32]188int hc_init_mem_structures(hc_t *instance)
[9351353]189{
190 assert(instance);
191#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
192 if (ret != EOK) { \
193 usb_log_error(message); \
194 if (instance->interrupt_code.cmds != NULL) \
195 free(instance->interrupt_code.cmds); \
196 return ret; \
197 } else (void) 0
198
199 /* Init interrupt code */
200 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
201 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
202 CHECK_RET_DEST_CMDS_RETURN(ret,
203 "Failed to allocate interrupt cmds space.\n");
204
205 {
206 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
207 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
208 interrupt_commands[0].addr =
209 (void*)&instance->registers->usbsts;
210 interrupt_commands[1].addr =
211 (void*)&instance->registers->usbsts;
212 instance->interrupt_code.cmdcount =
213 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
214 }
215
216 /* Init transfer lists */
[c01cd32]217 ret = hc_init_transfer_lists(instance);
[9351353]218 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
219 usb_log_debug("Initialized transfer lists.\n");
220
221 /* Init USB frame list page*/
222 instance->frame_list = get_page();
223 ret = instance ? EOK : ENOMEM;
224 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
225 usb_log_debug("Initialized frame list.\n");
226
227 /* Set all frames to point to the first queue head */
228 const uint32_t queue =
229 instance->transfers_interrupt.queue_head_pa
230 | LINK_POINTER_QUEUE_HEAD_FLAG;
231
232 unsigned i = 0;
233 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
234 instance->frame_list[i] = queue;
235 }
236
237 /* Init device keeper*/
[62ed5bc]238 usb_device_keeper_init(&instance->manager);
[9351353]239 usb_log_debug("Initialized device manager.\n");
240
241 return EOK;
242#undef CHECK_RET_DEST_CMDS_RETURN
243}
244/*----------------------------------------------------------------------------*/
[17ceb72]245/** Initialize UHCI hc transfer lists.
[9351353]246 *
247 * @param[in] instance UHCI structure to use.
248 * @return Error code
249 * @note Should be called only once on any structure.
[17ceb72]250 *
251 * Initializes transfer lists and sets them in one chain to support proper
252 * USB scheduling. Sets pointer table for quick access.
[9351353]253 */
[c01cd32]254int hc_init_transfer_lists(hc_t *instance)
[9351353]255{
256 assert(instance);
257#define CHECK_RET_CLEAR_RETURN(ret, message...) \
258 if (ret != EOK) { \
259 usb_log_error(message); \
260 transfer_list_fini(&instance->transfers_bulk_full); \
261 transfer_list_fini(&instance->transfers_control_full); \
262 transfer_list_fini(&instance->transfers_control_slow); \
263 transfer_list_fini(&instance->transfers_interrupt); \
264 return ret; \
265 } else (void) 0
266
267 /* initialize TODO: check errors */
268 int ret;
269 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
270 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
271
272 ret = transfer_list_init(
273 &instance->transfers_control_full, "CONTROL_FULL");
274 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
275
276 ret = transfer_list_init(
277 &instance->transfers_control_slow, "CONTROL_SLOW");
278 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
279
280 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
281 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
282
283 transfer_list_set_next(&instance->transfers_control_full,
284 &instance->transfers_bulk_full);
285 transfer_list_set_next(&instance->transfers_control_slow,
286 &instance->transfers_control_full);
287 transfer_list_set_next(&instance->transfers_interrupt,
288 &instance->transfers_control_slow);
289
290 /*FSBR*/
291#ifdef FSBR
292 transfer_list_set_next(&instance->transfers_bulk_full,
293 &instance->transfers_control_full);
294#endif
295
296 /* Assign pointers to be used during scheduling */
297 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
298 &instance->transfers_interrupt;
299 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
300 &instance->transfers_interrupt;
301 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
302 &instance->transfers_control_full;
303 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
304 &instance->transfers_control_slow;
305 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
306 &instance->transfers_bulk_full;
307
308 return EOK;
309#undef CHECK_RET_CLEAR_RETURN
310}
311/*----------------------------------------------------------------------------*/
[17ceb72]312/** Schedule batch for execution.
[9351353]313 *
314 * @param[in] instance UHCI structure to use.
315 * @param[in] batch Transfer batch to schedule.
316 * @return Error code
[17ceb72]317 *
318 * Checks for bandwidth availability and appends the batch to the proper queue.
[9351353]319 */
[c01cd32]320int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
[9351353]321{
322 assert(instance);
323 assert(batch);
324 const int low_speed = (batch->speed == USB_SPEED_LOW);
325 if (!allowed_usb_packet(
326 low_speed, batch->transfer_type, batch->max_packet_size)) {
327 usb_log_warning(
328 "Invalid USB packet specified %s SPEED %d %zu.\n",
329 low_speed ? "LOW" : "FULL" , batch->transfer_type,
330 batch->max_packet_size);
331 return ENOTSUP;
332 }
[17ceb72]333 /* TODO: check available bandwidth here */
[9351353]334
335 transfer_list_t *list =
336 instance->transfers[batch->speed][batch->transfer_type];
337 assert(list);
338 transfer_list_add_batch(list, batch);
339
340 return EOK;
341}
342/*----------------------------------------------------------------------------*/
[17ceb72]343/** Take action based on the interrupt cause.
[9351353]344 *
345 * @param[in] instance UHCI structure to use.
[17ceb72]346 * @param[in] status Value of the status register at the time of interrupt.
347 *
348 * Interrupt might indicate:
349 * - transaction completed, either by triggering IOC, SPD, or an error
350 * - some kind of device error
351 * - resume from suspend state (not implemented)
[9351353]352 */
[c01cd32]353void hc_interrupt(hc_t *instance, uint16_t status)
[9351353]354{
355 assert(instance);
[a963a68]356 /* TODO: Resume interrupts are not supported */
[9351353]357 /* Lower 2 bits are transaction error and transaction complete */
358 if (status & 0x3) {
359 transfer_list_remove_finished(&instance->transfers_interrupt);
360 transfer_list_remove_finished(&instance->transfers_control_slow);
361 transfer_list_remove_finished(&instance->transfers_control_full);
362 transfer_list_remove_finished(&instance->transfers_bulk_full);
363 }
[a963a68]364 /* bits 4 and 5 indicate hc error */
365 if (status & 0x18) {
[fcc525d]366 usb_log_error("UHCI hardware failure!.\n");
367 ++instance->hw_failures;
[a963a68]368 transfer_list_abort_all(&instance->transfers_interrupt);
369 transfer_list_abort_all(&instance->transfers_control_slow);
370 transfer_list_abort_all(&instance->transfers_control_full);
371 transfer_list_abort_all(&instance->transfers_bulk_full);
[fcc525d]372
373 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
374 /* reinitialize hw, this triggers virtual disconnect*/
[c01cd32]375 hc_init_hw(instance);
[fcc525d]376 } else {
377 usb_log_fatal("Too many UHCI hardware failures!.\n");
[c01cd32]378 hc_fini(instance);
[fcc525d]379 }
[a963a68]380 }
[9351353]381}
382/*----------------------------------------------------------------------------*/
383/** Polling function, emulates interrupts.
384 *
[17ceb72]385 * @param[in] arg UHCI hc structure to use.
386 * @return EOK (should never return)
[9351353]387 */
[c01cd32]388int hc_interrupt_emulator(void* arg)
[9351353]389{
390 usb_log_debug("Started interrupt emulator.\n");
[c01cd32]391 hc_t *instance = (hc_t*)arg;
[9351353]392 assert(instance);
393
394 while (1) {
395 /* read and ack interrupts */
396 uint16_t status = pio_read_16(&instance->registers->usbsts);
397 pio_write_16(&instance->registers->usbsts, 0x1f);
398 if (status != 0)
399 usb_log_debug2("UHCI status: %x.\n", status);
[c01cd32]400 hc_interrupt(instance, status);
[9351353]401 async_usleep(UHCI_CLEANER_TIMEOUT);
402 }
403 return EOK;
404}
405/*---------------------------------------------------------------------------*/
406/** Debug function, checks consistency of memory structures.
407 *
408 * @param[in] arg UHCI structure to use.
[17ceb72]409 * @return EOK (should never return)
[9351353]410 */
[c01cd32]411int hc_debug_checker(void *arg)
[9351353]412{
[c01cd32]413 hc_t *instance = (hc_t*)arg;
[9351353]414 assert(instance);
415
416#define QH(queue) \
417 instance->transfers_##queue.queue_head
418
419 while (1) {
420 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
421 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
422 const uint16_t intr =
423 pio_read_16(&instance->registers->usbintr);
424
425 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
426 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
427 cmd, sts, intr);
428 }
429
430 uintptr_t frame_list =
431 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
432 if (frame_list != addr_to_phys(instance->frame_list)) {
433 usb_log_debug("Framelist address: %p vs. %p.\n",
434 frame_list, addr_to_phys(instance->frame_list));
435 }
436
437 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
438
439 uintptr_t expected_pa = instance->frame_list[frnum]
440 & LINK_POINTER_ADDRESS_MASK;
441 uintptr_t real_pa = addr_to_phys(QH(interrupt));
442 if (expected_pa != real_pa) {
443 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
444 expected_pa, frnum, real_pa);
445 }
446
447 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
448 real_pa = addr_to_phys(QH(control_slow));
449 if (expected_pa != real_pa) {
450 usb_log_debug("Control Slow QH: %p vs. %p.\n",
451 expected_pa, real_pa);
452 }
453
454 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
455 real_pa = addr_to_phys(QH(control_full));
456 if (expected_pa != real_pa) {
457 usb_log_debug("Control Full QH: %p vs. %p.\n",
458 expected_pa, real_pa);
459 }
460
461 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
462 real_pa = addr_to_phys(QH(bulk_full));
463 if (expected_pa != real_pa ) {
464 usb_log_debug("Bulk QH: %p vs. %p.\n",
465 expected_pa, real_pa);
466 }
467 async_usleep(UHCI_DEBUGER_TIMEOUT);
468 }
469 return EOK;
470#undef QH
471}
472/*----------------------------------------------------------------------------*/
[17ceb72]473/** Check transfer packets, for USB validity
[9351353]474 *
475 * @param[in] low_speed Transfer speed.
476 * @param[in] transfer Transer type
477 * @param[in] size Maximum size of used packets
[17ceb72]478 * @return True if transaction is allowed by USB specs, false otherwise
[9351353]479 */
480bool allowed_usb_packet(
481 bool low_speed, usb_transfer_type_t transfer, size_t size)
482{
483 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
484 switch(transfer)
485 {
486 case USB_TRANSFER_ISOCHRONOUS:
487 return (!low_speed && size < 1024);
488 case USB_TRANSFER_INTERRUPT:
489 return size <= (low_speed ? 8 : 64);
490 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
491 return (size <= (low_speed ? 8 : 64));
492 case USB_TRANSFER_BULK: /* device specifies its own max size */
493 return (!low_speed && size <= 64);
494 }
495 return false;
496}
497/**
498 * @}
499 */
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