source: mainline/uspace/drv/uhci-hcd/hc.c@ 4fd3faf

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4fd3faf was 4fd3faf, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Use per endpoint communication mutex
  • Property mode set to 100644
File size: 16.1 KB
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[9351353]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[17ceb72]28/** @addtogroup drvusbuhcihc
[9351353]29 * @{
30 */
31/** @file
[17ceb72]32 * @brief UHCI Host controller driver routines
[9351353]33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
[c01cd32]44#include "hc.h"
[9351353]45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
[c01cd32]62static int hc_init_transfer_lists(hc_t *instance);
63static int hc_init_mem_structures(hc_t *instance);
64static void hc_init_hw(hc_t *instance);
[9351353]65
[c01cd32]66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
[391d55b]68#if 0
[c61338a]69static bool usb_is_allowed(
[9351353]70 bool low_speed, usb_transfer_type_t transfer, size_t size);
[391d55b]71#endif
[9351353]72/*----------------------------------------------------------------------------*/
[17ceb72]73/** Initialize UHCI hcd driver structure
[9351353]74 *
75 * @param[in] instance Memory place to initialize.
76 * @param[in] fun DDF function.
77 * @param[in] regs Address of I/O control registers.
78 * @param[in] size Size of I/O control registers.
79 * @return Error code.
80 * @note Should be called only once on any structure.
[17ceb72]81 *
82 * Initializes memory structures, starts up hw, and launches debugger and
83 * interrupt fibrils.
[9351353]84 */
[c01cd32]85int hc_init(hc_t *instance, ddf_fun_t *fun,
[ff34e5a]86 void *regs, size_t reg_size, bool interrupts)
[9351353]87{
88 assert(reg_size >= sizeof(regs_t));
89 int ret;
90
91#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
92 if (ret != EOK) { \
93 usb_log_error(message); \
94 if (instance->ddf_instance) \
95 ddf_fun_destroy(instance->ddf_instance); \
96 return ret; \
97 } else (void) 0
98
[ff34e5a]99 instance->hw_interrupts = interrupts;
[fcc525d]100 instance->hw_failures = 0;
101
[9351353]102 /* Setup UHCI function. */
103 instance->ddf_instance = fun;
104
105 /* allow access to hc control registers */
106 regs_t *io;
107 ret = pio_enable(regs, reg_size, (void**)&io);
108 CHECK_RET_DEST_FUN_RETURN(ret,
109 "Failed(%d) to gain access to registers at %p: %s.\n",
110 ret, str_error(ret), io);
111 instance->registers = io;
112 usb_log_debug("Device registers at %p(%u) accessible.\n",
113 io, reg_size);
114
[c01cd32]115 ret = hc_init_mem_structures(instance);
[9351353]116 CHECK_RET_DEST_FUN_RETURN(ret,
117 "Failed to initialize UHCI memory structures.\n");
118
[c01cd32]119 hc_init_hw(instance);
[ff34e5a]120 if (!interrupts) {
121 instance->cleaner =
[c01cd32]122 fibril_create(hc_interrupt_emulator, instance);
[ff34e5a]123 fibril_add_ready(instance->cleaner);
[7d6a676]124 } else {
125 /* TODO: enable interrupts here */
[ff34e5a]126 }
[9351353]127
[13b9cb5]128 instance->debug_checker =
[c01cd32]129 fibril_create(hc_debug_checker, instance);
[13b9cb5]130// fibril_add_ready(instance->debug_checker);
[9351353]131
132 return EOK;
133#undef CHECK_RET_DEST_FUN_RETURN
134}
135/*----------------------------------------------------------------------------*/
[17ceb72]136/** Initialize UHCI hc hw resources.
[9351353]137 *
138 * @param[in] instance UHCI structure to use.
[17ceb72]139 * For magic values see UHCI Design Guide
[9351353]140 */
[c01cd32]141void hc_init_hw(hc_t *instance)
[9351353]142{
143 assert(instance);
144 regs_t *registers = instance->registers;
145
146 /* Reset everything, who knows what touched it before us */
147 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
148 async_usleep(10000); /* 10ms according to USB spec */
149 pio_write_16(&registers->usbcmd, 0);
150
151 /* Reset hc, all states and counters */
152 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
153 do { async_usleep(10); }
154 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
155
[eb2a48a]156 /* Set frame to exactly 1ms */
157 pio_write_8(&registers->sofmod, 64);
158
159 /* Set frame list pointer */
[9351353]160 const uint32_t pa = addr_to_phys(instance->frame_list);
161 pio_write_32(&registers->flbaseadd, pa);
162
[ff34e5a]163 if (instance->hw_interrupts) {
164 /* Enable all interrupts, but resume interrupt */
165 pio_write_16(&instance->registers->usbintr,
166 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
167 }
[9351353]168
169 uint16_t status = pio_read_16(&registers->usbcmd);
170 if (status != 0)
171 usb_log_warning("Previous command value: %x.\n", status);
172
173 /* Start the hc with large(64B) packet FSBR */
174 pio_write_16(&registers->usbcmd,
175 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
176}
177/*----------------------------------------------------------------------------*/
[17ceb72]178/** Initialize UHCI hc memory structures.
[9351353]179 *
180 * @param[in] instance UHCI structure to use.
181 * @return Error code
182 * @note Should be called only once on any structure.
[17ceb72]183 *
184 * Structures:
185 * - interrupt code (I/O addressses are customized per instance)
186 * - transfer lists (queue heads need to be accessible by the hw)
187 * - frame list page (needs to be one UHCI hw accessible 4K page)
[9351353]188 */
[c01cd32]189int hc_init_mem_structures(hc_t *instance)
[9351353]190{
191 assert(instance);
192#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
193 if (ret != EOK) { \
194 usb_log_error(message); \
195 if (instance->interrupt_code.cmds != NULL) \
196 free(instance->interrupt_code.cmds); \
197 return ret; \
198 } else (void) 0
199
200 /* Init interrupt code */
201 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
202 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
203 CHECK_RET_DEST_CMDS_RETURN(ret,
204 "Failed to allocate interrupt cmds space.\n");
205
206 {
207 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
208 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
209 interrupt_commands[0].addr =
210 (void*)&instance->registers->usbsts;
211 interrupt_commands[1].addr =
212 (void*)&instance->registers->usbsts;
213 instance->interrupt_code.cmdcount =
214 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
215 }
216
217 /* Init transfer lists */
[c01cd32]218 ret = hc_init_transfer_lists(instance);
[9351353]219 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
220 usb_log_debug("Initialized transfer lists.\n");
221
222 /* Init USB frame list page*/
223 instance->frame_list = get_page();
224 ret = instance ? EOK : ENOMEM;
225 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
[001b152]226 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
[9351353]227
228 /* Set all frames to point to the first queue head */
229 const uint32_t queue =
230 instance->transfers_interrupt.queue_head_pa
231 | LINK_POINTER_QUEUE_HEAD_FLAG;
232
233 unsigned i = 0;
234 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
235 instance->frame_list[i] = queue;
236 }
237
238 /* Init device keeper*/
[62ed5bc]239 usb_device_keeper_init(&instance->manager);
[9351353]240 usb_log_debug("Initialized device manager.\n");
241
[6ce42e85]242 ret =
243 usb_endpoint_manager_init(&instance->ep_manager,
244 BANDWIDTH_AVAILABLE_USB11);
[d527a4e]245 assert(ret == EOK);
[a1313b8c]246
[9351353]247 return EOK;
248#undef CHECK_RET_DEST_CMDS_RETURN
249}
250/*----------------------------------------------------------------------------*/
[17ceb72]251/** Initialize UHCI hc transfer lists.
[9351353]252 *
253 * @param[in] instance UHCI structure to use.
254 * @return Error code
255 * @note Should be called only once on any structure.
[17ceb72]256 *
257 * Initializes transfer lists and sets them in one chain to support proper
258 * USB scheduling. Sets pointer table for quick access.
[9351353]259 */
[c01cd32]260int hc_init_transfer_lists(hc_t *instance)
[9351353]261{
262 assert(instance);
263#define CHECK_RET_CLEAR_RETURN(ret, message...) \
264 if (ret != EOK) { \
265 usb_log_error(message); \
266 transfer_list_fini(&instance->transfers_bulk_full); \
267 transfer_list_fini(&instance->transfers_control_full); \
268 transfer_list_fini(&instance->transfers_control_slow); \
269 transfer_list_fini(&instance->transfers_interrupt); \
270 return ret; \
271 } else (void) 0
272
273 /* initialize TODO: check errors */
274 int ret;
275 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
276 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
277
278 ret = transfer_list_init(
279 &instance->transfers_control_full, "CONTROL_FULL");
280 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
281
282 ret = transfer_list_init(
283 &instance->transfers_control_slow, "CONTROL_SLOW");
284 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
285
286 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
287 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
288
289 transfer_list_set_next(&instance->transfers_control_full,
290 &instance->transfers_bulk_full);
291 transfer_list_set_next(&instance->transfers_control_slow,
292 &instance->transfers_control_full);
293 transfer_list_set_next(&instance->transfers_interrupt,
294 &instance->transfers_control_slow);
295
296 /*FSBR*/
297#ifdef FSBR
298 transfer_list_set_next(&instance->transfers_bulk_full,
299 &instance->transfers_control_full);
300#endif
301
302 /* Assign pointers to be used during scheduling */
303 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
304 &instance->transfers_interrupt;
305 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
306 &instance->transfers_interrupt;
307 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
308 &instance->transfers_control_full;
309 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
310 &instance->transfers_control_slow;
311 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
312 &instance->transfers_bulk_full;
313
314 return EOK;
315#undef CHECK_RET_CLEAR_RETURN
316}
317/*----------------------------------------------------------------------------*/
[17ceb72]318/** Schedule batch for execution.
[9351353]319 *
320 * @param[in] instance UHCI structure to use.
321 * @param[in] batch Transfer batch to schedule.
322 * @return Error code
[17ceb72]323 *
324 * Checks for bandwidth availability and appends the batch to the proper queue.
[9351353]325 */
[c01cd32]326int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
[9351353]327{
328 assert(instance);
329 assert(batch);
330
331 transfer_list_t *list =
332 instance->transfers[batch->speed][batch->transfer_type];
333 assert(list);
334 transfer_list_add_batch(list, batch);
335
336 return EOK;
337}
338/*----------------------------------------------------------------------------*/
[17ceb72]339/** Take action based on the interrupt cause.
[9351353]340 *
341 * @param[in] instance UHCI structure to use.
[17ceb72]342 * @param[in] status Value of the status register at the time of interrupt.
343 *
344 * Interrupt might indicate:
345 * - transaction completed, either by triggering IOC, SPD, or an error
346 * - some kind of device error
347 * - resume from suspend state (not implemented)
[9351353]348 */
[c01cd32]349void hc_interrupt(hc_t *instance, uint16_t status)
[9351353]350{
351 assert(instance);
[1273b86c]352// status |= 1; //Uncomment to work around qemu hang
[a963a68]353 /* TODO: Resume interrupts are not supported */
[9351353]354 /* Lower 2 bits are transaction error and transaction complete */
355 if (status & 0x3) {
[1585c7e]356 LIST_INITIALIZE(done);
357 transfer_list_remove_finished(
358 &instance->transfers_interrupt, &done);
359 transfer_list_remove_finished(
360 &instance->transfers_control_slow, &done);
361 transfer_list_remove_finished(
362 &instance->transfers_control_full, &done);
363 transfer_list_remove_finished(
364 &instance->transfers_bulk_full, &done);
365
366 while (!list_empty(&done)) {
367 link_t *item = done.next;
368 list_remove(item);
369 usb_transfer_batch_t *batch =
370 list_get_instance(item, usb_transfer_batch_t, link);
[cd1cec3b]371 usb_transfer_batch_finish(batch);
[1585c7e]372 }
[9351353]373 }
[a963a68]374 /* bits 4 and 5 indicate hc error */
375 if (status & 0x18) {
[fcc525d]376 usb_log_error("UHCI hardware failure!.\n");
377 ++instance->hw_failures;
[a963a68]378 transfer_list_abort_all(&instance->transfers_interrupt);
379 transfer_list_abort_all(&instance->transfers_control_slow);
380 transfer_list_abort_all(&instance->transfers_control_full);
381 transfer_list_abort_all(&instance->transfers_bulk_full);
[fcc525d]382
383 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
384 /* reinitialize hw, this triggers virtual disconnect*/
[c01cd32]385 hc_init_hw(instance);
[fcc525d]386 } else {
387 usb_log_fatal("Too many UHCI hardware failures!.\n");
[c01cd32]388 hc_fini(instance);
[fcc525d]389 }
[a963a68]390 }
[9351353]391}
392/*----------------------------------------------------------------------------*/
393/** Polling function, emulates interrupts.
394 *
[17ceb72]395 * @param[in] arg UHCI hc structure to use.
396 * @return EOK (should never return)
[9351353]397 */
[c01cd32]398int hc_interrupt_emulator(void* arg)
[9351353]399{
400 usb_log_debug("Started interrupt emulator.\n");
[c01cd32]401 hc_t *instance = (hc_t*)arg;
[9351353]402 assert(instance);
403
404 while (1) {
405 /* read and ack interrupts */
406 uint16_t status = pio_read_16(&instance->registers->usbsts);
407 pio_write_16(&instance->registers->usbsts, 0x1f);
408 if (status != 0)
409 usb_log_debug2("UHCI status: %x.\n", status);
[c01cd32]410 hc_interrupt(instance, status);
[9351353]411 async_usleep(UHCI_CLEANER_TIMEOUT);
412 }
413 return EOK;
414}
415/*---------------------------------------------------------------------------*/
416/** Debug function, checks consistency of memory structures.
417 *
418 * @param[in] arg UHCI structure to use.
[17ceb72]419 * @return EOK (should never return)
[9351353]420 */
[c01cd32]421int hc_debug_checker(void *arg)
[9351353]422{
[c01cd32]423 hc_t *instance = (hc_t*)arg;
[9351353]424 assert(instance);
425
426#define QH(queue) \
427 instance->transfers_##queue.queue_head
428
429 while (1) {
430 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
431 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
432 const uint16_t intr =
433 pio_read_16(&instance->registers->usbintr);
434
435 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
436 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
437 cmd, sts, intr);
438 }
439
440 uintptr_t frame_list =
441 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
442 if (frame_list != addr_to_phys(instance->frame_list)) {
443 usb_log_debug("Framelist address: %p vs. %p.\n",
444 frame_list, addr_to_phys(instance->frame_list));
445 }
446
447 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
448
449 uintptr_t expected_pa = instance->frame_list[frnum]
450 & LINK_POINTER_ADDRESS_MASK;
451 uintptr_t real_pa = addr_to_phys(QH(interrupt));
452 if (expected_pa != real_pa) {
453 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
454 expected_pa, frnum, real_pa);
455 }
456
457 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
458 real_pa = addr_to_phys(QH(control_slow));
459 if (expected_pa != real_pa) {
460 usb_log_debug("Control Slow QH: %p vs. %p.\n",
461 expected_pa, real_pa);
462 }
463
464 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
465 real_pa = addr_to_phys(QH(control_full));
466 if (expected_pa != real_pa) {
467 usb_log_debug("Control Full QH: %p vs. %p.\n",
468 expected_pa, real_pa);
469 }
470
471 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
472 real_pa = addr_to_phys(QH(bulk_full));
473 if (expected_pa != real_pa ) {
474 usb_log_debug("Bulk QH: %p vs. %p.\n",
475 expected_pa, real_pa);
476 }
477 async_usleep(UHCI_DEBUGER_TIMEOUT);
478 }
479 return EOK;
480#undef QH
481}
482/*----------------------------------------------------------------------------*/
[c61338a]483/** Check transfers for USB validity
[9351353]484 *
485 * @param[in] low_speed Transfer speed.
486 * @param[in] transfer Transer type
[c61338a]487 * @param[in] size Size of data packets
[17ceb72]488 * @return True if transaction is allowed by USB specs, false otherwise
[9351353]489 */
[391d55b]490#if 0
[c61338a]491bool usb_is_allowed(
[9351353]492 bool low_speed, usb_transfer_type_t transfer, size_t size)
493{
494 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
495 switch(transfer)
496 {
497 case USB_TRANSFER_ISOCHRONOUS:
498 return (!low_speed && size < 1024);
499 case USB_TRANSFER_INTERRUPT:
500 return size <= (low_speed ? 8 : 64);
501 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
502 return (size <= (low_speed ? 8 : 64));
503 case USB_TRANSFER_BULK: /* device specifies its own max size */
504 return (!low_speed && size <= 64);
505 }
506 return false;
507}
[391d55b]508#endif
[9351353]509/**
510 * @}
511 */
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