| [17be8c2] | 1 | /*
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| 2 | * Copyright (c) 2012 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| [4122410] | 29 | /** @addtogroup amdm37x
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| [17be8c2] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Clock Control Clock Management IO register structure.
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| 34 | */
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| 35 | #ifndef AMDM37X_PRM_GLOBAL_REG_H
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| 36 | #define AMDM37X_PRM_GLOBAL_REG_H
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| [7ee7e6a] | 37 |
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| 38 | #include <ddi.h>
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| [17be8c2] | 39 | #include <macros.h>
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| 40 |
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| 41 | /* AM/DM37x TRM p.536 and p.615 */
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| 42 | #define GLOBAL_REG_PRM_BASE_ADDRESS 0x48307200
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| 43 | #define GLOBAL_REG_PRM_SIZE 65536
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| 44 |
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| 45 | /** Global Reg PRM register map
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| 46 | */
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| 47 | typedef struct {
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| [af60409] | 48 | PADD32(8);
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| [17be8c2] | 49 | struct {
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| 50 | ioport32_t smps_sa;
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| 51 | #define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
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| 52 | #define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_CREATE(x) (((x) & 0x7f) << 0)
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| 53 | #define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_GET(r) (r & 0x7f)
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| 54 | #define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
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| 55 | #define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_CREATE(x) (((x) & 0x7f) << 16)
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| 56 | #define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_GET(r) (((r) >> 16 ) & 0x7f)
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| 57 |
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| 58 | ioport32_t smps_vol_ra;
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| 59 | #define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_MASK (0xff << 0)
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| 60 | #define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_CREATE(x) (((x) & 0xff) << 0)
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| 61 | #define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_GET(r) (r & 0xff)
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| 62 | #define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_MASK (0xff << 16)
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| 63 | #define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_CREATE(x) (((x) & 0xff) << 16)
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| 64 | #define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_GET(r) (((r) >> 16 ) & 0xff)
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| 65 |
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| 66 | ioport32_t smps_cmd_ra;
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| 67 | #define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_MASK (0xff << 0)
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| 68 | #define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_CREATE(x) (((x) & 0xff) << 0)
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| 69 | #define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_GET(r) (r & 0xff)
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| 70 | #define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_MASK (0xff << 16)
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| 71 | #define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_CREATE(x) (((x) & 0xff) << 16)
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| 72 | #define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_GET(r) (((r) >> 16 ) & 0xff)
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| 73 |
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| 74 | ioport32_t cmd_val_0;
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| 75 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_MASK (0xff << 24)
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| 76 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_CREATE(x) (((x) & 0xff) << 24)
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| 77 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_GET(r) (((x) >> 24) & 0xff)
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| 78 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_MASK (0xff << 24)
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| 79 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_CREATE(x) (((x) & 0xff) << 24)
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| 80 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_GET(r) (((x) >> 24) & 0xff)
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| 81 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_MASK (0xff << 24)
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| 82 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_CREATE(x) (((x) & 0xff) << 24)
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| 83 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_GET(r) (((x) >> 24) & 0xff)
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| 84 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_MASK (0xff << 24)
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| 85 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_CREATE(x) (((x) & 0xff) << 24)
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| 86 | #define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_GET(r) (((x) >> 24) & 0xff)
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| 87 |
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| 88 | ioport32_t cmd_val_1;
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| 89 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_MASK (0xff << 24)
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| 90 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_CREATE(x) (((x) & 0xff) << 24)
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| 91 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_GET(r) (((x) >> 24) & 0xff)
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| 92 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_MASK (0xff << 24)
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| 93 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_CREATE(x) (((x) & 0xff) << 24)
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| 94 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_GET(r) (((x) >> 24) & 0xff)
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| 95 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_MASK (0xff << 24)
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| 96 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_CREATE(x) (((x) & 0xff) << 24)
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| 97 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_GET(r) (((x) >> 24) & 0xff)
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| 98 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_MASK (0xff << 24)
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| 99 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_CREATE(x) (((x) & 0xff) << 24)
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| 100 | #define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_GET(r) (((x) >> 24) & 0xff)
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| 101 |
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| 102 | ioport32_t ch_conf;
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| 103 | #define GLOBAL_REG_PRM_VC_CH_CONF_CMD1_FLAG (1 << 20)
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| 104 | #define GLOBAL_REG_PRM_VC_CH_CONF_RACEN1_FLAG (1 << 19)
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| 105 | #define GLOBAL_REG_PRM_VC_CH_CONF_RAC1_FLAG (1 << 18)
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| 106 | #define GLOBAL_REG_PRM_VC_CH_CONF_RAV1_FLAG (1 << 17)
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| 107 | #define GLOBAL_REG_PRM_VC_CH_CONF_SA1_FLAG (1 << 16)
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| 108 | #define GLOBAL_REG_PRM_VC_CH_CONF_CMD0_FLAG (1 << 4)
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| 109 | #define GLOBAL_REG_PRM_VC_CH_CONF_RACEN0_FLAG (1 << 3)
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| 110 | #define GLOBAL_REG_PRM_VC_CH_CONF_RAC0_FLAG (1 << 2)
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| 111 | #define GLOBAL_REG_PRM_VC_CH_CONF_RAV0_FLAG (1 << 1)
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| 112 | #define GLOBAL_REG_PRM_VC_CH_CONF_SA0_FLAG (1 << 0)
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| 113 |
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| 114 | ioport32_t i2c_cfg;
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| 115 | #define GLOBAL_REG_PRM_VC_I2C_CFG_HSMASTER_FLAG (1 << 5)
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| 116 | #define GLOBAL_REG_PRM_VC_I2C_CFG_SREN_FLAG (1 << 4)
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| 117 | #define GLOBAL_REG_PRM_VC_I2C_CFG_HSEN_FLAG (1 << 3)
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| 118 | #define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_MASK (0x3 << 0)
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| 119 | #define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_CREATE(x) ((x) & 0x3)
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| 120 | #define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_GET(r) ((r) & 0x3)
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| 121 |
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| 122 | ioport32_t bypass_val;
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| 123 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_VALID_FLAG (1 << 24)
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| 124 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_MASK (0xff << 16)
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| 125 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_CREATE(x) (((x) & 0xff) << 16)
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| 126 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_GET(r) (((r) >> 16) & 0xff)
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| 127 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_MASK (0xff << 8)
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| 128 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_CREATE(x) (((x) & 0xff) << 8)
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| 129 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_GET(r) (((r) >> 8) & 0xff)
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| 130 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_MASK (0x7f << 0)
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| 131 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_CREATE(x) (((x) & 0x7f) << 0)
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| 132 | #define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_GET(r) (((r) >> 0) & 0x7f)
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| 133 | } vc;
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| 134 |
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| [af60409] | 135 | PADD32(4);
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| [17be8c2] | 136 | ioport32_t rstctrl;
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| 137 | #define GLOBAL_REG_PRM_RSTCTRL_RST_DPLL3_FLAG (1 << 2)
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| 138 | #define GLOBAL_REG_PRM_RSTCTRL_RST_GS_FLAG (1 << 1)
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| 139 |
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| 140 | ioport32_t rsttime;
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| 141 | #define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_MASK (0x1f << 8)
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| 142 | #define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_CREATE(x) (((x) & 0x1f) << 8)
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| 143 | #define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_GET(r) (((r) >> 8) & 0x1f)
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| 144 | #define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_MASK (0xff << 0)
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| 145 | #define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_CREATE(x) (((x) & 0xff) << 0)
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| 146 | #define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_GET(r) (((r) >> 0) & 0xff)
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| 147 |
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| 148 | ioport32_t rstst;
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| 149 | #define GLOBAL_REG_PRM_RSTST_ICECRUSHER_RST_FLAG (1 << 10)
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| 150 | #define GLOBAL_REG_PRM_RSTST_ICEPICK_RST_FLAG (1 << 9)
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| 151 | #define GLOBAL_REG_PRM_RSTST_VDD2_VOLTAGE_MGR_RST_FLAG (1 << 8)
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| 152 | #define GLOBAL_REG_PRM_RSTST_VDD1_VOLTAGE_MGR_RST_FLAG (1 << 7)
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| 153 | #define GLOBAL_REG_PRM_RSTST_EXTERNAL_WARM_REST_FLAG (1 << 6)
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| 154 | #define GLOBAL_REG_PRM_RSTST_MPU_WD_RST_FLAG (1 << 4)
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| 155 | #define GLOBAL_REG_PRM_RSTST_GLOBAL_SW_RST_FLAG (1 << 1)
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| 156 | #define GLOBAL_REG_PRM_RSTST_GLOABL_COLD_RST_FLAG (1 << 0)
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| 157 |
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| [af60409] | 158 | PADD32(1);
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| [17be8c2] | 159 | ioport32_t volctrl;
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| 160 | #define GLOBAL_REG_PRM_VOLCTRL_SEL_VMODE_FLAG (1 << 4)
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| 161 | #define GLOBAL_REG_PRM_VOLCTRL_SEL_OFF_FLAG (1 << 3)
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| 162 | #define GLOBAL_REG_PRM_VOLCTRL_AUTO_OFF_FLAG (1 << 2)
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| 163 | #define GLOBAL_REG_PRM_VOLCTRL_AUTO_RET_FLAG (1 << 1)
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| 164 | #define GLOBAL_REG_PRM_VOLCTRL_AUTO_SLEEP_FLAG (1 << 0)
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| 165 |
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| 166 | ioport32_t sram_pcharge;
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| 167 | #define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_MASK (0xff)
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| 168 | #define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_CREATE(x) ((x) & 0xff)
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| 169 | #define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_GET(r) ((r) & 0xff)
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| 170 |
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| [af60409] | 171 | PADD32(2);
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| [17be8c2] | 172 | ioport32_t clksrc_ctrl;
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| 173 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_DPLL4_CLKINP_DIV_65_FLAG (1 << 8)
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| 174 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_MASK (0x3 << 6)
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| 175 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_1 (0x1 << 6)
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| 176 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_2 (0x2 << 6)
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| 177 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(r) (((r) >> 6) & 0x3)
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| 178 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_MASK (0x3 << 3)
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| 179 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_ON (0x0 << 3)
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| 180 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_SLEEP (0x1 << 3)
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| 181 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_RET (0x2 << 3)
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| 182 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_OFF (0x3 << 3)
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| 183 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_GET(r) (((r) >> 3) & 0x3)
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| 184 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_MASK (0x3 << 0)
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| 185 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_BYPASS (0x0 << 0)
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| 186 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_OSCILLATOR (0x1 << 0)
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| 187 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_UNKNOWN (0x3 << 0)
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| 188 | #define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_GET(r) (((r) >> 0) & 0x3)
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| 189 |
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| [af60409] | 190 | PADD32(3);
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| [17be8c2] | 191 | const ioport32_t obs;
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| 192 | #define GLOBAL_REG_PRM_OBS_OBS_BUS_MASK (0x3ff)
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| 193 |
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| [af60409] | 194 | PADD32(3);
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| [17be8c2] | 195 | ioport32_t voltsetup1;
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| 196 | #define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_MASK (0xff << 16)
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| 197 | #define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_CREATE(x) (((x) & 0xff) << 16)
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| 198 | #define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_GET(r) (((r) >> 16) & 0xff)
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| 199 | #define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_MASK (0xff << 0)
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| 200 | #define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_CREATE(x) (((x) & 0xff) << 0)
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| 201 | #define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_GET(r) (((r) >> 0) & 0xff)
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| 202 |
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| 203 | ioport32_t voltoffset;
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| 204 | #define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_MASK (0xffff << 0)
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| 205 | #define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_CREATE(x) (((x) & 0xffff) << 0)
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| 206 | #define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_GET(r) (((r) >> 0) & 0xffff)
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| 207 |
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| 208 | ioport32_t clksetup;
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| 209 | #define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_MASK (0xffff << 0)
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| 210 | #define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_CREATE(x) (((x) & 0xffff) << 0)
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| 211 | #define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_GET(r) (((r) >> 0) & 0xffff)
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| 212 |
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| 213 | ioport32_t polctrl;
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| 214 | #define GLOBAL_REG_PRM_POLCTRL_OFFMODE_POL_FLAG (1 << 3)
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| 215 | #define GLOBAL_REG_PRM_POLCTRL_CLKOUT_POL_FLAG (1 << 2)
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| 216 | #define GLOBAL_REG_PRM_POLCTRL_CLKREG_POL_FLAG (1 << 1)
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| 217 | #define GLOBAL_REG_PRM_POLCTRL_EXTVOL_POL_FLAG (1 << 0)
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| 218 |
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| 219 | ioport32_t voltsetup2;
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| 220 | #define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_MASK (0xffff << 0)
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| 221 | #define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_CREATE(x) (((x) & 0xffff) << 0)
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| 222 | #define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_GET(r) (((r) >> 0) & 0xffff)
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| 223 |
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| [af60409] | 224 | PADD32(3);
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| [17be8c2] | 225 | struct {
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| 226 | ioport32_t config;
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| 227 | #define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_MASK (0xff << 24)
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| 228 | #define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_CREATE(x) (((x) & 0xff) << 24)
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| 229 | #define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_GET(r) (((r) >> 0xff << 24)
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| 230 | #define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_MASK (0xff << 16)
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| 231 | #define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_CREATE(x) (((x) & 0xff) << 16)
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| 232 | #define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_GET(r) (((r) >> 0xff << 16)
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| 233 | #define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_MASK (0xff << 8)
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| 234 | #define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_CREATE(x) (((x) & 0xff) << 8)
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| 235 | #define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_GET(r) (((r) >> 0xff << 8)
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| 236 | #define GLOBAL_REG_PRM_VP_CONFIG_TIMEOUTEN_FLAG (1 << 3)
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| 237 | #define GLOBAL_REG_PRM_VP_CONFIG_INITVDD_FLAG (1 << 2)
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| 238 | #define GLOBAL_REG_PRM_VP_CONFIG_FORCEUPDATE_FLAG (1 << 1)
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| 239 | #define GLOBAL_REG_PRM_VP_CONFIG_VPENABLE_FLAG (1 << 0)
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| 240 |
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| 241 | ioport32_t vstepmin;
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| 242 | #define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_MASK (0xffff << 8)
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| 243 | #define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8)
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| 244 | #define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff)
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| 245 | #define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_MASK (0xff << 0)
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| 246 | #define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_CREATE(x) (((x)0xff << 0)
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| 247 | #define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_GET(r) (((r) >> 0) & 0xff)
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| 248 |
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| 249 | ioport32_t vstepmax;
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| 250 | #define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_MASK (0xffff << 8)
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| 251 | #define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8)
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| 252 | #define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff)
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| 253 | #define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_MASK (0xff << 0)
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| 254 | #define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_CREATE(x) (((x)0xff << 0)
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| 255 | #define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_GET(r) (((r) >> 0) & 0xff)
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| 256 |
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| 257 | ioport32_t vlimitto;
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| 258 | #define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_MASK (0xff << 24)
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| 259 | #define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_CREATE(x) (((x)0xff << 24)
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| 260 | #define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_GET(r) (((r) >> 24) & 0xff)
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| 261 | #define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_MASK (0xff << 16)
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| 262 | #define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_CREATE(x) (((x)0xff << 16)
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| 263 | #define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_GET(r) (((r) >> 16) & 0xff)
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| 264 | #define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_MASK (0xffff << 0)
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| 265 | #define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_CREATE(x) (((x)0xffff << 0)
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| 266 | #define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_GET(r) (((r) >> 0) & 0xffff)
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| 267 |
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| 268 | const ioport32_t voltage;
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| 269 | #define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_MASK (0xff)
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| 270 | #define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_GET(r) ((r) & 0xff)
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| 271 |
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| 272 | const ioport32_t status;
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| 273 | #define GLOBAL_REG_PRM_VP_STATUS_VPINIDLE_FLAG (1 << 0)
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| 274 |
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| [af60409] | 275 | PADD32(2);
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| [17be8c2] | 276 | } vp[2];
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| 277 |
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| 278 | ioport32_t ldo_abb_setup;
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| 279 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_IN_TRANSITION (1 << 6)
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| 280 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_MASK (0x3 << 3)
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| 281 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_BYPASS (0x0 << 3)
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| 282 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_FBB (0x2 << 3)
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| 283 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_OPP_CHANGE_FLAG (1 << 2)
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| 284 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_MASK (0x3 << 0)
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| 285 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_DEFAULT (0x0 << 0)
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| 286 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_FAST (0x1 << 0)
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| 287 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_NOMINAL (0x2 << 0)
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| 288 | #define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_SLOW (0x3 << 0)
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| 289 |
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| 290 | ioport32_t ldo_abb_ctrl;
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| 291 | #define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_MASK (0xff << 8)
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| 292 | #define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_CREATE(x) (((x) & 0xff) << 8)
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| 293 | #define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_GET(r) (((r) >> 8) & 0xff)
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| 294 | #define GLOBAL_REG_PRM_LDO_ABB_CTRL_ACTIVE_FBB_SEL_FLAG (1 << 2)
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| 295 | #define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2EN (1 << 0)
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| 296 | } global_reg_prm_regs_t;
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| 297 |
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| 298 | #endif
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| 299 | /**
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| 300 | * @}
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| 301 | */
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