source: mainline/uspace/drv/platform/amdm37x/amdm37x.c@ 9905da7

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1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @addtogroup amdm37x
31 * @{
32 */
33
34/** @file
35 */
36
37#include "amdm37x.h"
38
39#include <assert.h>
40#include <ddi.h>
41#include <ddf/log.h>
42#include <errno.h>
43#include <stdio.h>
44
45static void
46log_message(const volatile void *place, uint64_t val, volatile void *base, size_t size,
47 void *data, bool write)
48{
49 printf("PIO %s: %p(%p) %#" PRIx64 "\n", write ? "WRITE" : "READ",
50 (place - base) + data, place, val);
51}
52
53
54errno_t amdm37x_init(amdm37x_t *device, bool trace)
55{
56 assert(device);
57 errno_t ret = EOK;
58
59 ret = pio_enable((void *)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
60 (void **)&device->cm.usbhost);
61 if (ret != EOK)
62 return ret;
63
64 ret = pio_enable((void *)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
65 (void **)&device->cm.core);
66 if (ret != EOK)
67 return ret;
68
69 ret = pio_enable((void *)CLOCK_CONTROL_CM_BASE_ADDRESS,
70 CLOCK_CONTROL_CM_SIZE, (void **)&device->cm.clocks);
71 if (ret != EOK)
72 return ret;
73
74 ret = pio_enable((void *)MPU_CM_BASE_ADDRESS,
75 MPU_CM_SIZE, (void **)&device->cm.mpu);
76 if (ret != EOK)
77 return ret;
78
79 ret = pio_enable((void *)IVA2_CM_BASE_ADDRESS,
80 IVA2_CM_SIZE, (void **)&device->cm.iva2);
81 if (ret != EOK)
82 return ret;
83
84 ret = pio_enable((void *)CLOCK_CONTROL_PRM_BASE_ADDRESS,
85 CLOCK_CONTROL_PRM_SIZE, (void **)&device->prm.clocks);
86 if (ret != EOK)
87 return ret;
88
89 ret = pio_enable((void *)GLOBAL_REG_PRM_BASE_ADDRESS,
90 GLOBAL_REG_PRM_SIZE, (void **)&device->prm.global);
91 if (ret != EOK)
92 return ret;
93
94 ret = pio_enable((void *)AMDM37x_USBTLL_BASE_ADDRESS,
95 AMDM37x_USBTLL_SIZE, (void **)&device->tll);
96 if (ret != EOK)
97 return ret;
98
99 ret = pio_enable((void *)AMDM37x_UHH_BASE_ADDRESS,
100 AMDM37x_UHH_SIZE, (void **)&device->uhh);
101 if (ret != EOK)
102 return ret;
103
104 if (trace) {
105 pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log_message, (void *)AMDM37x_USBTLL_BASE_ADDRESS);
106 pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log_message, (void *)CLOCK_CONTROL_CM_BASE_ADDRESS);
107 pio_trace_enable(device->cm.core, CORE_CM_SIZE, log_message, (void *)CORE_CM_BASE_ADDRESS);
108 pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log_message, (void *)MPU_CM_BASE_ADDRESS);
109 pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log_message, (void *)IVA2_CM_BASE_ADDRESS);
110 pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log_message, (void *)USBHOST_CM_BASE_ADDRESS);
111 pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log_message, (void *)AMDM37x_UHH_BASE_ADDRESS);
112 pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log_message, (void *)CLOCK_CONTROL_PRM_BASE_ADDRESS);
113 pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log_message, (void *)GLOBAL_REG_PRM_BASE_ADDRESS);
114 }
115 return EOK;
116}
117
118
119/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
120 * @param device Register map.
121 *
122 * The idea is to get all DPLLs running and make hw control their power mode,
123 * based on the module requirements (module ICLKs and FCLKs).
124 */
125void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device)
126{
127 assert(device);
128 /*
129 * Get SYS_CLK value, it is used as reference clock by all DPLLs,
130 * NFI who sets this or why it is set to specific value.
131 */
132 const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) &
133 CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
134 const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
135 const unsigned base_freq = sys_clk_freq_kHz(osc_clk) /
136 GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
137 ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
138 base_freq / 1000, base_freq % 1000);
139
140
141 /*
142 * DPLL1 provides MPU(CPU) clock.
143 * It uses SYS_CLK as reference clock and core clock (DPLL3) as
144 * high frequency bypass (MPU then runs on L3 interconnect freq).
145 * It should be setup by fw or u-boot.
146 */
147 mpu_cm_regs_t *mpu = device->cm.mpu;
148
149 /* Current MPU frequency. */
150 if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
151 if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
152 /* DPLL active and locked */
153 const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
154 const unsigned multiplier =
155 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) >>
156 MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
157 const unsigned divisor =
158 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) >>
159 MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT;
160 const unsigned divisor2 =
161 (pio_read_32(&mpu->clksel2_pll) &
162 MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
163 if (multiplier && divisor && divisor2) {
164 /** See AMDM37x TRM p. 300 for the formula */
165 const unsigned freq =
166 ((base_freq * multiplier) / (divisor + 1)) /
167 divisor2;
168 ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
169 freq / 1000, freq % 1000);
170 } else {
171 ddf_msg(LVL_WARN, "Frequency divisor and/or "
172 "multiplier value invalid: %d %d %d",
173 multiplier, divisor, divisor2);
174 }
175 } else {
176 /* DPLL in LP bypass mode */
177 const unsigned divisor =
178 MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
179 pio_read_32(&mpu->clksel1_pll));
180 ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
181 " CORE CLK / %d MHz", divisor);
182 }
183 } else {
184 ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
185 }
186 // TODO: Enable this (automatic MPU downclocking):
187#if 0
188 /*
189 * Enable low power bypass mode, this will take effect the next lock or
190 * relock sequence.
191 */
192 //TODO: We might need to force re-lock after enabling this
193 pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
194 /* Enable automatic relocking */
195 pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
196#endif
197
198 /*
199 * DPLL2 provides IVA(video acceleration) clock.
200 * It uses SYS_CLK as reference clokc and core clock (DPLL3) as
201 * high frequency bypass (IVA runs on L3 freq).
202 */
203 // TODO: We can probably turn this off entirely. IVA is left unused.
204 /*
205 * Enable low power bypass mode, this will take effect the next lock or
206 * relock sequence.
207 */
208 //TODO: We might need to force re-lock after enabling this
209 pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
210 /* Enable automatic relocking */
211 pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
212
213 /*
214 * DPLL3 provides tons of clocks:
215 * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
216 * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
217 * bypass. It should be setup by fw or u-boot as it controls critical
218 * interconnects.
219 */
220 if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
221 /* DPLL active and locked */
222 const uint32_t reg =
223 pio_read_32(&device->cm.clocks->clksel1_pll);
224 const unsigned multiplier =
225 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
226 const unsigned divisor =
227 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
228 const unsigned divisor2 =
229 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
230 if (multiplier && divisor && divisor2) {
231 /** See AMDM37x TRM p. 300 for the formula */
232 const unsigned freq =
233 ((base_freq * multiplier) / (divisor + 1)) / divisor2;
234 ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
235 freq / 1000, freq % 1000);
236 const unsigned l3_div =
237 pio_read_32(&device->cm.core->clksel) &
238 CORE_CM_CLKSEL_CLKSEL_L3_MASK;
239 if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
240 l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
241 ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
242 (freq / l3_div) / 1000,
243 (freq / l3_div) % 1000);
244 } else {
245 ddf_msg(LVL_WARN, "L3 interface clock divisor is"
246 " invalid: %d", l3_div);
247 }
248 } else {
249 ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
250 "multiplier value invalid: %d %d %d",
251 multiplier, divisor, divisor2);
252 }
253 } else {
254 ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
255 " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
256 }
257
258 /* Set DPLL3 to automatic to save power */
259 pio_change_32(&device->cm.clocks->autoidle_pll,
260 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
261 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
262
263 /*
264 * DPLL4 provides peripheral domain clocks:
265 * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
266 * It uses SYS_CLK as reference clock and low frequency bypass.
267 * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
268 * we can probably turn this off entirely (DSS is still non-functional).
269 */
270 /* Set DPLL4 to automatic to save power */
271 pio_change_32(&device->cm.clocks->autoidle_pll,
272 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
273 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
274
275 /*
276 * DPLL5 provide peripheral domain clocks: 120M_FCLK.
277 * It uses SYS_CLK as reference clock and low frequency bypass.
278 * 120M clock is used by HS USB and USB TLL.
279 */
280 // TODO setup DPLL5
281 if ((pio_read_32(&device->cm.clocks->clken2_pll) &
282 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) !=
283 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
284 /*
285 * Compute divisors and multiplier
286 * See AMDM37x TRM p. 300 for the formula
287 */
288 // TODO: base_freq does not have to be rounded to Mhz
289 // (that's why I used KHz as unit).
290 const unsigned mult = 120;
291 const unsigned div = (base_freq / 1000) - 1;
292 const unsigned div2 = 1;
293 if (((base_freq % 1000) != 0) || (div > 127)) {
294 ddf_msg(LVL_ERROR, "Rounding error, or divisor to big "
295 "freq: %d, div: %d", base_freq, div);
296 return;
297 }
298 assert(div <= 127);
299
300 /* Set multiplier */
301 pio_change_32(&device->cm.clocks->clksel4_pll,
302 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
303 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
304
305 /* Set DPLL divisor */
306 pio_change_32(&device->cm.clocks->clksel4_pll,
307 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
308 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
309
310 /* Set output clock divisor */
311 pio_change_32(&device->cm.clocks->clksel5_pll,
312 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
313 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
314
315 /* Start DPLL5 */
316 pio_change_32(&device->cm.clocks->clken2_pll,
317 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
318 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
319
320 }
321 /* Set DPLL5 to automatic to save power */
322 pio_change_32(&device->cm.clocks->autoidle2_pll,
323 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
324 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
325}
326
327/** Enable/disable function and interface clocks for USBTLL and USBHOST.
328 * @param device Register map.
329 * @param on True to switch clocks on.
330 */
331void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled)
332{
333 if (enabled) {
334 /* Enable interface and function clock for USB TLL */
335 pio_set_32(&device->cm.core->fclken3,
336 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
337 pio_set_32(&device->cm.core->iclken3,
338 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
339
340 /* Enable interface and function clock for USB hosts */
341 pio_set_32(&device->cm.usbhost->fclken,
342 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
343 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
344 pio_set_32(&device->cm.usbhost->iclken,
345 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
346#if 0
347 printf("DPLL5 (and everything else) should be on: %"
348 PRIx32 " %" PRIx32 ".\n",
349 pio_read_32(&device->cm.clocks->idlest_ckgen),
350 pio_read_32(&device->cm.clocks->idlest2_ckgen));
351#endif
352 } else {
353 /* Disable interface and function clock for USB hosts */
354 pio_clear_32(&device->cm.usbhost->iclken,
355 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
356 pio_clear_32(&device->cm.usbhost->fclken,
357 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
358 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
359
360 /* Disable interface and function clock for USB TLL */
361 pio_clear_32(&device->cm.core->iclken3,
362 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
363 pio_clear_32(&device->cm.core->fclken3,
364 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
365 }
366}
367
368/** Initialize USB TLL port connections.
369 *
370 * Different modes are on page 3312 of the Manual Figure 22-34.
371 * Select mode than can operate in FS/LS.
372 */
373errno_t amdm37x_usb_tll_init(amdm37x_t *device)
374{
375 /* Check access */
376 if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) {
377 ddf_msg(LVL_ERROR, "USB TLL is not accessible");
378 return EIO;
379 }
380
381 /* Reset USB TLL */
382 pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
383 ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
384 while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG))
385 ;
386 ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
387
388 /* Setup idle mode (smart idle) */
389 pio_change_32(&device->tll->sysconfig,
390 TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
391 TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
392
393 /* Smart idle for UHH */
394 pio_change_32(&device->uhh->sysconfig,
395 UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
396 UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
397
398 /*
399 * Set all ports to go through TLL(UTMI)
400 * Direct connection can only work in HS mode
401 */
402 pio_set_32(&device->uhh->hostconfig,
403 UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
404 UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
405 UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
406
407 /* What is this? */
408 pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
409
410 for (unsigned i = 0; i < 3; ++i) {
411 /*
412 * Serial mode is the only one capable of FS/LS operation.
413 * Select FS/LS mode, no idea what the difference is
414 * one of bidirectional modes might be good choice
415 * 2 = 3pin bidi phy.
416 */
417 pio_change_32(&device->tll->channel_conf[i],
418 TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
419 TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
420 TLL_CHANNEL_CONF_CHANMODE_MASK |
421 TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
422 }
423 return EOK;
424}
425
426/**
427 * @}
428 */
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