source: mainline/uspace/drv/platform/amdm37x/amdm37x.c@ 7c3fb9b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7c3fb9b was 7c3fb9b, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix block comment formatting (ccheck).
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1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @defgroup amdm37x TI AM/DM37x platform driver.
31 * @brief HelenOS TI AM/DM37x platform driver.
32 * @{
33 */
34
35/** @file
36 */
37
38#include "amdm37x.h"
39
40#include <assert.h>
41#include <ddi.h>
42#include <ddf/log.h>
43#include <errno.h>
44#include <stdio.h>
45
46static void
47log_message(const volatile void *place, uint64_t val, volatile void *base, size_t size,
48 void *data, bool write)
49{
50 printf("PIO %s: %p(%p) %#" PRIx64 "\n", write ? "WRITE" : "READ",
51 (place - base) + data, place, val);
52}
53
54
55errno_t amdm37x_init(amdm37x_t *device, bool trace)
56{
57 assert(device);
58 errno_t ret = EOK;
59
60 ret = pio_enable((void *)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
61 (void **)&device->cm.usbhost);
62 if (ret != EOK)
63 return ret;
64
65 ret = pio_enable((void *)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
66 (void **)&device->cm.core);
67 if (ret != EOK)
68 return ret;
69
70 ret = pio_enable((void *)CLOCK_CONTROL_CM_BASE_ADDRESS,
71 CLOCK_CONTROL_CM_SIZE, (void **)&device->cm.clocks);
72 if (ret != EOK)
73 return ret;
74
75 ret = pio_enable((void *)MPU_CM_BASE_ADDRESS,
76 MPU_CM_SIZE, (void **)&device->cm.mpu);
77 if (ret != EOK)
78 return ret;
79
80 ret = pio_enable((void *)IVA2_CM_BASE_ADDRESS,
81 IVA2_CM_SIZE, (void **)&device->cm.iva2);
82 if (ret != EOK)
83 return ret;
84
85 ret = pio_enable((void *)CLOCK_CONTROL_PRM_BASE_ADDRESS,
86 CLOCK_CONTROL_PRM_SIZE, (void **)&device->prm.clocks);
87 if (ret != EOK)
88 return ret;
89
90 ret = pio_enable((void *)GLOBAL_REG_PRM_BASE_ADDRESS,
91 GLOBAL_REG_PRM_SIZE, (void **)&device->prm.global);
92 if (ret != EOK)
93 return ret;
94
95 ret = pio_enable((void *)AMDM37x_USBTLL_BASE_ADDRESS,
96 AMDM37x_USBTLL_SIZE, (void **)&device->tll);
97 if (ret != EOK)
98 return ret;
99
100 ret = pio_enable((void *)AMDM37x_UHH_BASE_ADDRESS,
101 AMDM37x_UHH_SIZE, (void **)&device->uhh);
102 if (ret != EOK)
103 return ret;
104
105 if (trace) {
106 pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log_message, (void *)AMDM37x_USBTLL_BASE_ADDRESS);
107 pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log_message, (void *)CLOCK_CONTROL_CM_BASE_ADDRESS);
108 pio_trace_enable(device->cm.core, CORE_CM_SIZE, log_message, (void *)CORE_CM_BASE_ADDRESS);
109 pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log_message, (void *)MPU_CM_BASE_ADDRESS);
110 pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log_message, (void *)IVA2_CM_BASE_ADDRESS);
111 pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log_message, (void *)USBHOST_CM_BASE_ADDRESS);
112 pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log_message, (void *)AMDM37x_UHH_BASE_ADDRESS);
113 pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log_message, (void *)CLOCK_CONTROL_PRM_BASE_ADDRESS);
114 pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log_message, (void *)GLOBAL_REG_PRM_BASE_ADDRESS);
115 }
116 return EOK;
117}
118
119
120/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
121 * @param device Register map.
122 *
123 * The idea is to get all DPLLs running and make hw control their power mode,
124 * based on the module requirements (module ICLKs and FCLKs).
125 */
126void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device)
127{
128 assert(device);
129 /*
130 * Get SYS_CLK value, it is used as reference clock by all DPLLs,
131 * NFI who sets this or why it is set to specific value.
132 */
133 const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) &
134 CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
135 const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
136 const unsigned base_freq = sys_clk_freq_kHz(osc_clk) /
137 GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
138 ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
139 base_freq / 1000, base_freq % 1000);
140
141
142 /*
143 * DPLL1 provides MPU(CPU) clock.
144 * It uses SYS_CLK as reference clock and core clock (DPLL3) as
145 * high frequency bypass (MPU then runs on L3 interconnect freq).
146 * It should be setup by fw or u-boot.
147 */
148 mpu_cm_regs_t *mpu = device->cm.mpu;
149
150 /* Current MPU frequency. */
151 if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
152 if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
153 /* DPLL active and locked */
154 const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
155 const unsigned multiplier =
156 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) >>
157 MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
158 const unsigned divisor =
159 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) >>
160 MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT;
161 const unsigned divisor2 =
162 (pio_read_32(&mpu->clksel2_pll) &
163 MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
164 if (multiplier && divisor && divisor2) {
165 /** See AMDM37x TRM p. 300 for the formula */
166 const unsigned freq =
167 ((base_freq * multiplier) / (divisor + 1)) /
168 divisor2;
169 ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
170 freq / 1000, freq % 1000);
171 } else {
172 ddf_msg(LVL_WARN, "Frequency divisor and/or "
173 "multiplier value invalid: %d %d %d",
174 multiplier, divisor, divisor2);
175 }
176 } else {
177 /* DPLL in LP bypass mode */
178 const unsigned divisor =
179 MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
180 pio_read_32(&mpu->clksel1_pll));
181 ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
182 " CORE CLK / %d MHz", divisor);
183 }
184 } else {
185 ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
186 }
187 // TODO: Enable this (automatic MPU downclocking):
188#if 0
189 /*
190 * Enable low power bypass mode, this will take effect the next lock or
191 * relock sequence.
192 */
193 //TODO: We might need to force re-lock after enabling this
194 pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
195 /* Enable automatic relocking */
196 pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
197#endif
198
199 /*
200 * DPLL2 provides IVA(video acceleration) clock.
201 * It uses SYS_CLK as reference clokc and core clock (DPLL3) as
202 * high frequency bypass (IVA runs on L3 freq).
203 */
204 // TODO: We can probably turn this off entirely. IVA is left unused.
205 /*
206 * Enable low power bypass mode, this will take effect the next lock or
207 * relock sequence.
208 */
209 //TODO: We might need to force re-lock after enabling this
210 pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
211 /* Enable automatic relocking */
212 pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
213
214 /*
215 * DPLL3 provides tons of clocks:
216 * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
217 * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
218 * bypass. It should be setup by fw or u-boot as it controls critical
219 * interconnects.
220 */
221 if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
222 /* DPLL active and locked */
223 const uint32_t reg =
224 pio_read_32(&device->cm.clocks->clksel1_pll);
225 const unsigned multiplier =
226 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
227 const unsigned divisor =
228 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
229 const unsigned divisor2 =
230 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
231 if (multiplier && divisor && divisor2) {
232 /** See AMDM37x TRM p. 300 for the formula */
233 const unsigned freq =
234 ((base_freq * multiplier) / (divisor + 1)) / divisor2;
235 ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
236 freq / 1000, freq % 1000);
237 const unsigned l3_div =
238 pio_read_32(&device->cm.core->clksel) &
239 CORE_CM_CLKSEL_CLKSEL_L3_MASK;
240 if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
241 l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
242 ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
243 (freq / l3_div) / 1000,
244 (freq / l3_div) % 1000);
245 } else {
246 ddf_msg(LVL_WARN, "L3 interface clock divisor is"
247 " invalid: %d", l3_div);
248 }
249 } else {
250 ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
251 "multiplier value invalid: %d %d %d",
252 multiplier, divisor, divisor2);
253 }
254 } else {
255 ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
256 " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
257 }
258
259 /* Set DPLL3 to automatic to save power */
260 pio_change_32(&device->cm.clocks->autoidle_pll,
261 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
262 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
263
264 /*
265 * DPLL4 provides peripheral domain clocks:
266 * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
267 * It uses SYS_CLK as reference clock and low frequency bypass.
268 * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
269 * we can probably turn this off entirely (DSS is still non-functional).
270 */
271 /* Set DPLL4 to automatic to save power */
272 pio_change_32(&device->cm.clocks->autoidle_pll,
273 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
274 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
275
276 /*
277 * DPLL5 provide peripheral domain clocks: 120M_FCLK.
278 * It uses SYS_CLK as reference clock and low frequency bypass.
279 * 120M clock is used by HS USB and USB TLL.
280 */
281 // TODO setup DPLL5
282 if ((pio_read_32(&device->cm.clocks->clken2_pll) &
283 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) !=
284 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
285 /*
286 * Compute divisors and multiplier
287 * See AMDM37x TRM p. 300 for the formula
288 */
289 // TODO: base_freq does not have to be rounded to Mhz
290 // (that's why I used KHz as unit).
291 const unsigned mult = 120;
292 const unsigned div = (base_freq / 1000) - 1;
293 const unsigned div2 = 1;
294 if (((base_freq % 1000) != 0) || (div > 127)) {
295 ddf_msg(LVL_ERROR, "Rounding error, or divisor to big "
296 "freq: %d, div: %d", base_freq, div);
297 return;
298 }
299 assert(div <= 127);
300
301 /* Set multiplier */
302 pio_change_32(&device->cm.clocks->clksel4_pll,
303 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
304 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
305
306 /* Set DPLL divisor */
307 pio_change_32(&device->cm.clocks->clksel4_pll,
308 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
309 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
310
311 /* Set output clock divisor */
312 pio_change_32(&device->cm.clocks->clksel5_pll,
313 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
314 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
315
316 /* Start DPLL5 */
317 pio_change_32(&device->cm.clocks->clken2_pll,
318 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
319 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
320
321 }
322 /* Set DPLL5 to automatic to save power */
323 pio_change_32(&device->cm.clocks->autoidle2_pll,
324 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
325 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
326}
327
328/** Enable/disable function and interface clocks for USBTLL and USBHOST.
329 * @param device Register map.
330 * @param on True to switch clocks on.
331 */
332void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled)
333{
334 if (enabled) {
335 /* Enable interface and function clock for USB TLL */
336 pio_set_32(&device->cm.core->fclken3,
337 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
338 pio_set_32(&device->cm.core->iclken3,
339 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
340
341 /* Enable interface and function clock for USB hosts */
342 pio_set_32(&device->cm.usbhost->fclken,
343 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
344 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
345 pio_set_32(&device->cm.usbhost->iclken,
346 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
347#if 0
348 printf("DPLL5 (and everything else) should be on: %"
349 PRIx32 " %" PRIx32 ".\n",
350 pio_read_32(&device->cm.clocks->idlest_ckgen),
351 pio_read_32(&device->cm.clocks->idlest2_ckgen));
352#endif
353 } else {
354 /* Disable interface and function clock for USB hosts */
355 pio_clear_32(&device->cm.usbhost->iclken,
356 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
357 pio_clear_32(&device->cm.usbhost->fclken,
358 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
359 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
360
361 /* Disable interface and function clock for USB TLL */
362 pio_clear_32(&device->cm.core->iclken3,
363 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
364 pio_clear_32(&device->cm.core->fclken3,
365 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
366 }
367}
368
369/** Initialize USB TLL port connections.
370 *
371 * Different modes are on page 3312 of the Manual Figure 22-34.
372 * Select mode than can operate in FS/LS.
373 */
374errno_t amdm37x_usb_tll_init(amdm37x_t *device)
375{
376 /* Check access */
377 if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) {
378 ddf_msg(LVL_ERROR, "USB TLL is not accessible");
379 return EIO;
380 }
381
382 /* Reset USB TLL */
383 pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
384 ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
385 while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG))
386 ;
387 ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
388
389 /* Setup idle mode (smart idle) */
390 pio_change_32(&device->tll->sysconfig,
391 TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
392 TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
393
394 /* Smart idle for UHH */
395 pio_change_32(&device->uhh->sysconfig,
396 UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
397 UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
398
399 /*
400 * Set all ports to go through TLL(UTMI)
401 * Direct connection can only work in HS mode
402 */
403 pio_set_32(&device->uhh->hostconfig,
404 UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
405 UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
406 UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
407
408 /* What is this? */
409 pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
410
411 for (unsigned i = 0; i < 3; ++i) {
412 /*
413 * Serial mode is the only one capable of FS/LS operation.
414 * Select FS/LS mode, no idea what the difference is
415 * one of bidirectional modes might be good choice
416 * 2 = 3pin bidi phy.
417 */
418 pio_change_32(&device->tll->channel_conf[i],
419 TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
420 TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
421 TLL_CHANNEL_CONF_CHANMODE_MASK |
422 TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
423 }
424 return EOK;
425}
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