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source: mainline/uspace/drv/platform/amdm37x/amdm37x.c@ 901b302

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ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export

Last change on this file since 901b302 was 09ab0a9a, checked in by Jiri Svoboda <jiri@…>, 7 years ago
Fix vertical spacing with new Ccheck revision.
Property mode set to `100644`
File size: 15.2 KB

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[7a6d91b]	1	/*
	2	* Copyright (c) 2012 Jan Vesely
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions
	7	* are met:
	8	*
	9	* - Redistributions of source code must retain the above copyright
	10	* notice, this list of conditions and the following disclaimer.
	11	* - Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	* - The name of the author may not be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	27	*/
	28
	29	/**
[4122410]	30	* @addtogroup amdm37x
[7a6d91b]	31	* @{
	32	*/
	33
	34	/** @file
	35	*/
	36
	37	#include "amdm37x.h"
	38
	39	#include <assert.h>
	40	#include <ddi.h>
	41	#include <ddf/log.h>
	42	#include <errno.h>
	43	#include <stdio.h>
	44
[aa537a5a]	45	static void
[81b1db8]	46	log_message(const volatile void place, uint64_t val, volatile void base, size_t size,
[aa537a5a]	47	void *data, bool write)
[7a6d91b]	48	{
[18b6a88]	49	printf("PIO %s: %p(%p) %#" PRIx64 "\n", write ? "WRITE" : "READ",
[7a6d91b]	50	(place - base) + data, place, val);
	51	}
	52
[b7fd2a0]	53	errno_t amdm37x_init(amdm37x_t *device, bool trace)
[7a6d91b]	54	{
	55	assert(device);
[b7fd2a0]	56	errno_t ret = EOK;
[7a6d91b]	57
[18b6a88]	58	ret = pio_enable((void *)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
	59	(void **)&device->cm.usbhost);
[7a6d91b]	60	if (ret != EOK)
	61	return ret;
	62
[18b6a88]	63	ret = pio_enable((void *)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
	64	(void **)&device->cm.core);
[7a6d91b]	65	if (ret != EOK)
	66	return ret;
	67
[18b6a88]	68	ret = pio_enable((void *)CLOCK_CONTROL_CM_BASE_ADDRESS,
	69	CLOCK_CONTROL_CM_SIZE, (void **)&device->cm.clocks);
[7a6d91b]	70	if (ret != EOK)
	71	return ret;
	72
[18b6a88]	73	ret = pio_enable((void *)MPU_CM_BASE_ADDRESS,
	74	MPU_CM_SIZE, (void **)&device->cm.mpu);
[7a6d91b]	75	if (ret != EOK)
	76	return ret;
	77
[18b6a88]	78	ret = pio_enable((void *)IVA2_CM_BASE_ADDRESS,
	79	IVA2_CM_SIZE, (void **)&device->cm.iva2);
[7a6d91b]	80	if (ret != EOK)
	81	return ret;
	82
[18b6a88]	83	ret = pio_enable((void *)CLOCK_CONTROL_PRM_BASE_ADDRESS,
	84	CLOCK_CONTROL_PRM_SIZE, (void **)&device->prm.clocks);
[7a6d91b]	85	if (ret != EOK)
	86	return ret;
	87
[18b6a88]	88	ret = pio_enable((void *)GLOBAL_REG_PRM_BASE_ADDRESS,
	89	GLOBAL_REG_PRM_SIZE, (void **)&device->prm.global);
[7a6d91b]	90	if (ret != EOK)
	91	return ret;
	92
[18b6a88]	93	ret = pio_enable((void *)AMDM37x_USBTLL_BASE_ADDRESS,
	94	AMDM37x_USBTLL_SIZE, (void **)&device->tll);
[7a6d91b]	95	if (ret != EOK)
	96	return ret;
	97
[18b6a88]	98	ret = pio_enable((void *)AMDM37x_UHH_BASE_ADDRESS,
	99	AMDM37x_UHH_SIZE, (void **)&device->uhh);
[7a6d91b]	100	if (ret != EOK)
	101	return ret;
	102
	103	if (trace) {
[18b6a88]	104	pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log_message, (void *)AMDM37x_USBTLL_BASE_ADDRESS);
	105	pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log_message, (void *)CLOCK_CONTROL_CM_BASE_ADDRESS);
	106	pio_trace_enable(device->cm.core, CORE_CM_SIZE, log_message, (void *)CORE_CM_BASE_ADDRESS);
	107	pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log_message, (void *)MPU_CM_BASE_ADDRESS);
	108	pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log_message, (void *)IVA2_CM_BASE_ADDRESS);
	109	pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log_message, (void *)USBHOST_CM_BASE_ADDRESS);
	110	pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log_message, (void *)AMDM37x_UHH_BASE_ADDRESS);
	111	pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log_message, (void *)CLOCK_CONTROL_PRM_BASE_ADDRESS);
	112	pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log_message, (void *)GLOBAL_REG_PRM_BASE_ADDRESS);
[7a6d91b]	113	}
	114	return EOK;
	115	}
	116
	117	/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
	118	* @param device Register map.
	119	*
	120	* The idea is to get all DPLLs running and make hw control their power mode,
	121	* based on the module requirements (module ICLKs and FCLKs).
	122	*/
	123	void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device)
	124	{
	125	assert(device);
[7c3fb9b]	126	/*
	127	* Get SYS_CLK value, it is used as reference clock by all DPLLs,
	128	* NFI who sets this or why it is set to specific value.
	129	*/
[18b6a88]	130	const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) &
	131	CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
[7a6d91b]	132	const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
[18b6a88]	133	const unsigned base_freq = sys_clk_freq_kHz(osc_clk) /
	134	GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
[7a6d91b]	135	ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
	136	base_freq / 1000, base_freq % 1000);
	137
[7c3fb9b]	138	/*
	139	* DPLL1 provides MPU(CPU) clock.
[7a6d91b]	140	* It uses SYS_CLK as reference clock and core clock (DPLL3) as
	141	* high frequency bypass (MPU then runs on L3 interconnect freq).
[7c3fb9b]	142	* It should be setup by fw or u-boot.
	143	*/
[7a6d91b]	144	mpu_cm_regs_t *mpu = device->cm.mpu;
	145
	146	/* Current MPU frequency. */
	147	if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
	148	if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
	149	/* DPLL active and locked */
	150	const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
	151	const unsigned multiplier =
[18b6a88]	152	(reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) >>
	153	MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
[7a6d91b]	154	const unsigned divisor =
[18b6a88]	155	(reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) >>
	156	MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT;
[7a6d91b]	157	const unsigned divisor2 =
[18b6a88]	158	(pio_read_32(&mpu->clksel2_pll) &
	159	MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
[7a6d91b]	160	if (multiplier && divisor && divisor2) {
	161	/** See AMDM37x TRM p. 300 for the formula */
	162	const unsigned freq =
[18b6a88]	163	((base_freq * multiplier) / (divisor + 1)) /
	164	divisor2;
[7a6d91b]	165	ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
	166	freq / 1000, freq % 1000);
	167	} else {
	168	ddf_msg(LVL_WARN, "Frequency divisor and/or "
	169	"multiplier value invalid: %d %d %d",
	170	multiplier, divisor, divisor2);
	171	}
	172	} else {
	173	/* DPLL in LP bypass mode */
	174	const unsigned divisor =
	175	MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
[18b6a88]	176	pio_read_32(&mpu->clksel1_pll));
[7a6d91b]	177	ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
	178	" CORE CLK / %d MHz", divisor);
	179	}
	180	} else {
	181	ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
	182	}
	183	// TODO: Enable this (automatic MPU downclocking):
	184	#if 0
[7c3fb9b]	185	/*
	186	* Enable low power bypass mode, this will take effect the next lock or
	187	* relock sequence.
	188	*/
[7a6d91b]	189	//TODO: We might need to force re-lock after enabling this
	190	pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
	191	/* Enable automatic relocking */
	192	pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
	193	#endif
	194
[7c3fb9b]	195	/*
	196	* DPLL2 provides IVA(video acceleration) clock.
[7a6d91b]	197	* It uses SYS_CLK as reference clokc and core clock (DPLL3) as
	198	* high frequency bypass (IVA runs on L3 freq).
	199	*/
	200	// TODO: We can probably turn this off entirely. IVA is left unused.
[7c3fb9b]	201	/*
	202	* Enable low power bypass mode, this will take effect the next lock or
	203	* relock sequence.
	204	*/
[7a6d91b]	205	//TODO: We might need to force re-lock after enabling this
	206	pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
	207	/* Enable automatic relocking */
	208	pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
	209
[7c3fb9b]	210	/*
	211	* DPLL3 provides tons of clocks:
[7a6d91b]	212	* CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
	213	* and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
	214	* bypass. It should be setup by fw or u-boot as it controls critical
	215	* interconnects.
	216	*/
	217	if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
	218	/* DPLL active and locked */
	219	const uint32_t reg =
	220	pio_read_32(&device->cm.clocks->clksel1_pll);
	221	const unsigned multiplier =
	222	CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
	223	const unsigned divisor =
	224	CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
	225	const unsigned divisor2 =
	226	CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
	227	if (multiplier && divisor && divisor2) {
	228	/** See AMDM37x TRM p. 300 for the formula */
	229	const unsigned freq =
	230	((base_freq * multiplier) / (divisor + 1)) / divisor2;
	231	ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
	232	freq / 1000, freq % 1000);
	233	const unsigned l3_div =
[18b6a88]	234	pio_read_32(&device->cm.core->clksel) &
	235	CORE_CM_CLKSEL_CLKSEL_L3_MASK;
[7a6d91b]	236	if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 \|\|
	237	l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
	238	ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
	239	(freq / l3_div) / 1000,
	240	(freq / l3_div) % 1000);
	241	} else {
[18b6a88]	242	ddf_msg(LVL_WARN, "L3 interface clock divisor is"
[7a6d91b]	243	" invalid: %d", l3_div);
	244	}
	245	} else {
	246	ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
	247	"multiplier value invalid: %d %d %d",
	248	multiplier, divisor, divisor2);
	249	}
	250	} else {
	251	ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
[18b6a88]	252	" frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
[7a6d91b]	253	}
	254
	255	/* Set DPLL3 to automatic to save power */
	256	pio_change_32(&device->cm.clocks->autoidle_pll,
	257	CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
	258	CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
	259
[7c3fb9b]	260	/*
	261	* DPLL4 provides peripheral domain clocks:
[7a6d91b]	262	* CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
	263	* It uses SYS_CLK as reference clock and low frequency bypass.
	264	* 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
	265	* we can probably turn this off entirely (DSS is still non-functional).
	266	*/
	267	/* Set DPLL4 to automatic to save power */
	268	pio_change_32(&device->cm.clocks->autoidle_pll,
	269	CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
	270	CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
	271
[7c3fb9b]	272	/*
	273	* DPLL5 provide peripheral domain clocks: 120M_FCLK.
[7a6d91b]	274	* It uses SYS_CLK as reference clock and low frequency bypass.
	275	* 120M clock is used by HS USB and USB TLL.
	276	*/
	277	// TODO setup DPLL5
[18b6a88]	278	if ((pio_read_32(&device->cm.clocks->clken2_pll) &
	279	CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) !=
	280	CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
[7c3fb9b]	281	/*
	282	* Compute divisors and multiplier
	283	* See AMDM37x TRM p. 300 for the formula
	284	*/
[0f2c80a]	285	// TODO: base_freq does not have to be rounded to Mhz
	286	// (that's why I used KHz as unit).
	287	const unsigned mult = 120;
	288	const unsigned div = (base_freq / 1000) - 1;
[7a6d91b]	289	const unsigned div2 = 1;
[18b6a88]	290	if (((base_freq % 1000) != 0) \|\| (div > 127)) {
[0f2c80a]	291	ddf_msg(LVL_ERROR, "Rounding error, or divisor to big "
	292	"freq: %d, div: %d", base_freq, div);
	293	return;
[84239b1]	294	}
[0f2c80a]	295	assert(div <= 127);
[7a6d91b]	296
	297	/* Set multiplier */
	298	pio_change_32(&device->cm.clocks->clksel4_pll,
	299	CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
	300	CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
	301
	302	/* Set DPLL divisor */
	303	pio_change_32(&device->cm.clocks->clksel4_pll,
	304	CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
	305	CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
	306
	307	/* Set output clock divisor */
	308	pio_change_32(&device->cm.clocks->clksel5_pll,
	309	CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
	310	CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
	311
	312	/* Start DPLL5 */
	313	pio_change_32(&device->cm.clocks->clken2_pll,
	314	CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
	315	CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
	316
	317	}
	318	/* Set DPLL5 to automatic to save power */
	319	pio_change_32(&device->cm.clocks->autoidle2_pll,
	320	CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
	321	CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
	322	}
	323
	324	/** Enable/disable function and interface clocks for USBTLL and USBHOST.
	325	* @param device Register map.
	326	* @param on True to switch clocks on.
	327	*/
	328	void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled)
	329	{
	330	if (enabled) {
	331	/* Enable interface and function clock for USB TLL */
	332	pio_set_32(&device->cm.core->fclken3,
	333	CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
	334	pio_set_32(&device->cm.core->iclken3,
	335	CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
	336
	337	/* Enable interface and function clock for USB hosts */
	338	pio_set_32(&device->cm.usbhost->fclken,
	339	USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG \|
	340	USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
	341	pio_set_32(&device->cm.usbhost->iclken,
	342	USBHOST_CM_ICLKEN_EN_USBHOST, 5);
	343	#if 0
	344	printf("DPLL5 (and everything else) should be on: %"
[18b6a88]	345	PRIx32 " %" PRIx32 ".\n",
[7a6d91b]	346	pio_read_32(&device->cm.clocks->idlest_ckgen),
	347	pio_read_32(&device->cm.clocks->idlest2_ckgen));
	348	#endif
	349	} else {
	350	/* Disable interface and function clock for USB hosts */
	351	pio_clear_32(&device->cm.usbhost->iclken,
	352	USBHOST_CM_ICLKEN_EN_USBHOST, 5);
	353	pio_clear_32(&device->cm.usbhost->fclken,
	354	USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG \|
	355	USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
	356
	357	/* Disable interface and function clock for USB TLL */
	358	pio_clear_32(&device->cm.core->iclken3,
	359	CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
	360	pio_clear_32(&device->cm.core->fclken3,
	361	CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
	362	}
	363	}
	364
	365	/** Initialize USB TLL port connections.
	366	*
	367	* Different modes are on page 3312 of the Manual Figure 22-34.
	368	* Select mode than can operate in FS/LS.
	369	*/
[b7fd2a0]	370	errno_t amdm37x_usb_tll_init(amdm37x_t *device)
[7a6d91b]	371	{
	372	/* Check access */
	373	if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) {
	374	ddf_msg(LVL_ERROR, "USB TLL is not accessible");
	375	return EIO;
	376	}
	377
	378	/* Reset USB TLL */
	379	pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
	380	ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
[18b6a88]	381	while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG))
	382	;
[7a6d91b]	383	ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
	384
	385	/* Setup idle mode (smart idle) */
	386	pio_change_32(&device->tll->sysconfig,
	387	TLL_SYSCONFIG_CLOCKACTIVITY_FLAG \| TLL_SYSCONFIG_AUTOIDLE_FLAG \|
	388	TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
	389
	390	/* Smart idle for UHH */
	391	pio_change_32(&device->uhh->sysconfig,
	392	UHH_SYSCONFIG_CLOCKACTIVITY_FLAG \| UHH_SYSCONFIG_AUTOIDLE_FLAG \|
	393	UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
	394
[7c3fb9b]	395	/*
	396	* Set all ports to go through TLL(UTMI)
	397	* Direct connection can only work in HS mode
	398	*/
[7a6d91b]	399	pio_set_32(&device->uhh->hostconfig,
	400	UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG \|
	401	UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG \|
	402	UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
	403
	404	/* What is this? */
	405	pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
	406
	407	for (unsigned i = 0; i < 3; ++i) {
[7c3fb9b]	408	/*
	409	* Serial mode is the only one capable of FS/LS operation.
[7a6d91b]	410	* Select FS/LS mode, no idea what the difference is
	411	* one of bidirectional modes might be good choice
[7c3fb9b]	412	* 2 = 3pin bidi phy.
	413	*/
[7a6d91b]	414	pio_change_32(&device->tll->channel_conf[i],
	415	TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE \|
	416	TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
	417	TLL_CHANNEL_CONF_CHANMODE_MASK \|
	418	TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
	419	}
	420	return EOK;
	421	}
[4122410]	422
	423	/**
	424	* @}
	425	*/

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