[7a6d91b] | 1 | /*
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| 2 | * Copyright (c) 2012 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /**
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[4122410] | 30 | * @addtogroup amdm37x
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[7a6d91b] | 31 | * @{
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| 32 | */
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| 33 |
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| 34 | /** @file
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| 35 | */
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| 36 |
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| 37 | #include "amdm37x.h"
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| 38 |
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| 39 | #include <assert.h>
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| 40 | #include <ddi.h>
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| 41 | #include <ddf/log.h>
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| 42 | #include <errno.h>
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| 43 | #include <stdio.h>
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| 44 |
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[aa537a5a] | 45 | static void
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[81b1db8] | 46 | log_message(const volatile void *place, uint64_t val, volatile void *base, size_t size,
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[aa537a5a] | 47 | void *data, bool write)
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[7a6d91b] | 48 | {
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[18b6a88] | 49 | printf("PIO %s: %p(%p) %#" PRIx64 "\n", write ? "WRITE" : "READ",
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[7a6d91b] | 50 | (place - base) + data, place, val);
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| 51 | }
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| 52 |
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[b7fd2a0] | 53 | errno_t amdm37x_init(amdm37x_t *device, bool trace)
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[7a6d91b] | 54 | {
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| 55 | assert(device);
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[b7fd2a0] | 56 | errno_t ret = EOK;
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[7a6d91b] | 57 |
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[18b6a88] | 58 | ret = pio_enable((void *)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
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| 59 | (void **)&device->cm.usbhost);
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[7a6d91b] | 60 | if (ret != EOK)
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| 61 | return ret;
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| 62 |
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[18b6a88] | 63 | ret = pio_enable((void *)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
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| 64 | (void **)&device->cm.core);
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[7a6d91b] | 65 | if (ret != EOK)
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| 66 | return ret;
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| 67 |
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[18b6a88] | 68 | ret = pio_enable((void *)CLOCK_CONTROL_CM_BASE_ADDRESS,
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| 69 | CLOCK_CONTROL_CM_SIZE, (void **)&device->cm.clocks);
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[7a6d91b] | 70 | if (ret != EOK)
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| 71 | return ret;
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| 72 |
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[18b6a88] | 73 | ret = pio_enable((void *)MPU_CM_BASE_ADDRESS,
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| 74 | MPU_CM_SIZE, (void **)&device->cm.mpu);
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[7a6d91b] | 75 | if (ret != EOK)
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| 76 | return ret;
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| 77 |
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[18b6a88] | 78 | ret = pio_enable((void *)IVA2_CM_BASE_ADDRESS,
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| 79 | IVA2_CM_SIZE, (void **)&device->cm.iva2);
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[7a6d91b] | 80 | if (ret != EOK)
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| 81 | return ret;
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| 82 |
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[18b6a88] | 83 | ret = pio_enable((void *)CLOCK_CONTROL_PRM_BASE_ADDRESS,
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| 84 | CLOCK_CONTROL_PRM_SIZE, (void **)&device->prm.clocks);
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[7a6d91b] | 85 | if (ret != EOK)
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| 86 | return ret;
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| 87 |
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[18b6a88] | 88 | ret = pio_enable((void *)GLOBAL_REG_PRM_BASE_ADDRESS,
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| 89 | GLOBAL_REG_PRM_SIZE, (void **)&device->prm.global);
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[7a6d91b] | 90 | if (ret != EOK)
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| 91 | return ret;
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| 92 |
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[18b6a88] | 93 | ret = pio_enable((void *)AMDM37x_USBTLL_BASE_ADDRESS,
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| 94 | AMDM37x_USBTLL_SIZE, (void **)&device->tll);
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[7a6d91b] | 95 | if (ret != EOK)
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| 96 | return ret;
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| 97 |
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[18b6a88] | 98 | ret = pio_enable((void *)AMDM37x_UHH_BASE_ADDRESS,
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| 99 | AMDM37x_UHH_SIZE, (void **)&device->uhh);
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[7a6d91b] | 100 | if (ret != EOK)
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| 101 | return ret;
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| 102 |
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| 103 | if (trace) {
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[18b6a88] | 104 | pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log_message, (void *)AMDM37x_USBTLL_BASE_ADDRESS);
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| 105 | pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log_message, (void *)CLOCK_CONTROL_CM_BASE_ADDRESS);
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| 106 | pio_trace_enable(device->cm.core, CORE_CM_SIZE, log_message, (void *)CORE_CM_BASE_ADDRESS);
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| 107 | pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log_message, (void *)MPU_CM_BASE_ADDRESS);
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| 108 | pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log_message, (void *)IVA2_CM_BASE_ADDRESS);
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| 109 | pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log_message, (void *)USBHOST_CM_BASE_ADDRESS);
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| 110 | pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log_message, (void *)AMDM37x_UHH_BASE_ADDRESS);
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| 111 | pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log_message, (void *)CLOCK_CONTROL_PRM_BASE_ADDRESS);
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| 112 | pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log_message, (void *)GLOBAL_REG_PRM_BASE_ADDRESS);
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[7a6d91b] | 113 | }
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| 114 | return EOK;
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| 115 | }
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| 116 |
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| 117 | /** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
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| 118 | * @param device Register map.
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| 119 | *
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| 120 | * The idea is to get all DPLLs running and make hw control their power mode,
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| 121 | * based on the module requirements (module ICLKs and FCLKs).
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| 122 | */
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| 123 | void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device)
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| 124 | {
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| 125 | assert(device);
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[7c3fb9b] | 126 | /*
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| 127 | * Get SYS_CLK value, it is used as reference clock by all DPLLs,
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| 128 | * NFI who sets this or why it is set to specific value.
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| 129 | */
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[18b6a88] | 130 | const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) &
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| 131 | CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
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[7a6d91b] | 132 | const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
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[18b6a88] | 133 | const unsigned base_freq = sys_clk_freq_kHz(osc_clk) /
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| 134 | GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
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[7a6d91b] | 135 | ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
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| 136 | base_freq / 1000, base_freq % 1000);
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| 137 |
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[7c3fb9b] | 138 | /*
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| 139 | * DPLL1 provides MPU(CPU) clock.
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[7a6d91b] | 140 | * It uses SYS_CLK as reference clock and core clock (DPLL3) as
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| 141 | * high frequency bypass (MPU then runs on L3 interconnect freq).
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[7c3fb9b] | 142 | * It should be setup by fw or u-boot.
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| 143 | */
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[7a6d91b] | 144 | mpu_cm_regs_t *mpu = device->cm.mpu;
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| 145 |
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| 146 | /* Current MPU frequency. */
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| 147 | if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
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| 148 | if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
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| 149 | /* DPLL active and locked */
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| 150 | const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
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| 151 | const unsigned multiplier =
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[18b6a88] | 152 | (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) >>
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| 153 | MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
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[7a6d91b] | 154 | const unsigned divisor =
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[18b6a88] | 155 | (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) >>
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| 156 | MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT;
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[7a6d91b] | 157 | const unsigned divisor2 =
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[18b6a88] | 158 | (pio_read_32(&mpu->clksel2_pll) &
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| 159 | MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
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[7a6d91b] | 160 | if (multiplier && divisor && divisor2) {
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| 161 | /** See AMDM37x TRM p. 300 for the formula */
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| 162 | const unsigned freq =
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[18b6a88] | 163 | ((base_freq * multiplier) / (divisor + 1)) /
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| 164 | divisor2;
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[7a6d91b] | 165 | ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
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| 166 | freq / 1000, freq % 1000);
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| 167 | } else {
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| 168 | ddf_msg(LVL_WARN, "Frequency divisor and/or "
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| 169 | "multiplier value invalid: %d %d %d",
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| 170 | multiplier, divisor, divisor2);
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| 171 | }
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| 172 | } else {
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| 173 | /* DPLL in LP bypass mode */
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| 174 | const unsigned divisor =
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| 175 | MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
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[18b6a88] | 176 | pio_read_32(&mpu->clksel1_pll));
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[7a6d91b] | 177 | ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
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| 178 | " CORE CLK / %d MHz", divisor);
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| 179 | }
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| 180 | } else {
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| 181 | ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
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| 182 | }
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| 183 | // TODO: Enable this (automatic MPU downclocking):
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| 184 | #if 0
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[7c3fb9b] | 185 | /*
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| 186 | * Enable low power bypass mode, this will take effect the next lock or
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| 187 | * relock sequence.
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| 188 | */
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[7a6d91b] | 189 | //TODO: We might need to force re-lock after enabling this
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| 190 | pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
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| 191 | /* Enable automatic relocking */
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| 192 | pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
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| 193 | #endif
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| 194 |
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[7c3fb9b] | 195 | /*
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| 196 | * DPLL2 provides IVA(video acceleration) clock.
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[7a6d91b] | 197 | * It uses SYS_CLK as reference clokc and core clock (DPLL3) as
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| 198 | * high frequency bypass (IVA runs on L3 freq).
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| 199 | */
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| 200 | // TODO: We can probably turn this off entirely. IVA is left unused.
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[7c3fb9b] | 201 | /*
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| 202 | * Enable low power bypass mode, this will take effect the next lock or
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| 203 | * relock sequence.
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| 204 | */
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[7a6d91b] | 205 | //TODO: We might need to force re-lock after enabling this
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| 206 | pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
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| 207 | /* Enable automatic relocking */
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| 208 | pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
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| 209 |
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[7c3fb9b] | 210 | /*
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| 211 | * DPLL3 provides tons of clocks:
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[7a6d91b] | 212 | * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
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| 213 | * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
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| 214 | * bypass. It should be setup by fw or u-boot as it controls critical
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| 215 | * interconnects.
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| 216 | */
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| 217 | if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
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| 218 | /* DPLL active and locked */
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| 219 | const uint32_t reg =
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| 220 | pio_read_32(&device->cm.clocks->clksel1_pll);
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| 221 | const unsigned multiplier =
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| 222 | CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
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| 223 | const unsigned divisor =
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| 224 | CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
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| 225 | const unsigned divisor2 =
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| 226 | CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
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| 227 | if (multiplier && divisor && divisor2) {
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| 228 | /** See AMDM37x TRM p. 300 for the formula */
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| 229 | const unsigned freq =
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| 230 | ((base_freq * multiplier) / (divisor + 1)) / divisor2;
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| 231 | ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
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| 232 | freq / 1000, freq % 1000);
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| 233 | const unsigned l3_div =
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[18b6a88] | 234 | pio_read_32(&device->cm.core->clksel) &
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| 235 | CORE_CM_CLKSEL_CLKSEL_L3_MASK;
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[7a6d91b] | 236 | if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
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| 237 | l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
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| 238 | ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
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| 239 | (freq / l3_div) / 1000,
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| 240 | (freq / l3_div) % 1000);
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| 241 | } else {
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[18b6a88] | 242 | ddf_msg(LVL_WARN, "L3 interface clock divisor is"
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[7a6d91b] | 243 | " invalid: %d", l3_div);
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| 244 | }
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| 245 | } else {
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| 246 | ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
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| 247 | "multiplier value invalid: %d %d %d",
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| 248 | multiplier, divisor, divisor2);
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| 249 | }
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| 250 | } else {
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| 251 | ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
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[18b6a88] | 252 | " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
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[7a6d91b] | 253 | }
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| 254 |
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| 255 | /* Set DPLL3 to automatic to save power */
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| 256 | pio_change_32(&device->cm.clocks->autoidle_pll,
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| 257 | CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
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| 258 | CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
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| 259 |
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[7c3fb9b] | 260 | /*
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| 261 | * DPLL4 provides peripheral domain clocks:
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[7a6d91b] | 262 | * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
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| 263 | * It uses SYS_CLK as reference clock and low frequency bypass.
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| 264 | * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
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| 265 | * we can probably turn this off entirely (DSS is still non-functional).
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| 266 | */
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| 267 | /* Set DPLL4 to automatic to save power */
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| 268 | pio_change_32(&device->cm.clocks->autoidle_pll,
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| 269 | CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
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| 270 | CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
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| 271 |
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[7c3fb9b] | 272 | /*
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| 273 | * DPLL5 provide peripheral domain clocks: 120M_FCLK.
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[7a6d91b] | 274 | * It uses SYS_CLK as reference clock and low frequency bypass.
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| 275 | * 120M clock is used by HS USB and USB TLL.
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| 276 | */
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| 277 | // TODO setup DPLL5
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[18b6a88] | 278 | if ((pio_read_32(&device->cm.clocks->clken2_pll) &
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| 279 | CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) !=
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| 280 | CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
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[7c3fb9b] | 281 | /*
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| 282 | * Compute divisors and multiplier
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| 283 | * See AMDM37x TRM p. 300 for the formula
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| 284 | */
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[0f2c80a] | 285 | // TODO: base_freq does not have to be rounded to Mhz
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| 286 | // (that's why I used KHz as unit).
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| 287 | const unsigned mult = 120;
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| 288 | const unsigned div = (base_freq / 1000) - 1;
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[7a6d91b] | 289 | const unsigned div2 = 1;
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[18b6a88] | 290 | if (((base_freq % 1000) != 0) || (div > 127)) {
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[0f2c80a] | 291 | ddf_msg(LVL_ERROR, "Rounding error, or divisor to big "
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| 292 | "freq: %d, div: %d", base_freq, div);
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| 293 | return;
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[84239b1] | 294 | }
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[0f2c80a] | 295 | assert(div <= 127);
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[7a6d91b] | 296 |
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| 297 | /* Set multiplier */
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| 298 | pio_change_32(&device->cm.clocks->clksel4_pll,
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| 299 | CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
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| 300 | CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
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| 301 |
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| 302 | /* Set DPLL divisor */
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| 303 | pio_change_32(&device->cm.clocks->clksel4_pll,
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| 304 | CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
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| 305 | CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
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| 306 |
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| 307 | /* Set output clock divisor */
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| 308 | pio_change_32(&device->cm.clocks->clksel5_pll,
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| 309 | CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
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| 310 | CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
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| 311 |
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| 312 | /* Start DPLL5 */
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| 313 | pio_change_32(&device->cm.clocks->clken2_pll,
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| 314 | CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
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| 315 | CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
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| 316 |
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| 317 | }
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| 318 | /* Set DPLL5 to automatic to save power */
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| 319 | pio_change_32(&device->cm.clocks->autoidle2_pll,
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| 320 | CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
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| 321 | CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
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| 322 | }
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| 323 |
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| 324 | /** Enable/disable function and interface clocks for USBTLL and USBHOST.
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| 325 | * @param device Register map.
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| 326 | * @param on True to switch clocks on.
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| 327 | */
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| 328 | void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled)
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| 329 | {
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| 330 | if (enabled) {
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| 331 | /* Enable interface and function clock for USB TLL */
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| 332 | pio_set_32(&device->cm.core->fclken3,
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| 333 | CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
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| 334 | pio_set_32(&device->cm.core->iclken3,
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| 335 | CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
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| 336 |
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| 337 | /* Enable interface and function clock for USB hosts */
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| 338 | pio_set_32(&device->cm.usbhost->fclken,
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| 339 | USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
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| 340 | USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
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| 341 | pio_set_32(&device->cm.usbhost->iclken,
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| 342 | USBHOST_CM_ICLKEN_EN_USBHOST, 5);
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| 343 | #if 0
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| 344 | printf("DPLL5 (and everything else) should be on: %"
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[18b6a88] | 345 | PRIx32 " %" PRIx32 ".\n",
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[7a6d91b] | 346 | pio_read_32(&device->cm.clocks->idlest_ckgen),
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| 347 | pio_read_32(&device->cm.clocks->idlest2_ckgen));
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| 348 | #endif
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| 349 | } else {
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| 350 | /* Disable interface and function clock for USB hosts */
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| 351 | pio_clear_32(&device->cm.usbhost->iclken,
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| 352 | USBHOST_CM_ICLKEN_EN_USBHOST, 5);
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| 353 | pio_clear_32(&device->cm.usbhost->fclken,
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| 354 | USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
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| 355 | USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
|
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| 356 |
|
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| 357 | /* Disable interface and function clock for USB TLL */
|
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| 358 | pio_clear_32(&device->cm.core->iclken3,
|
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| 359 | CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
|
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| 360 | pio_clear_32(&device->cm.core->fclken3,
|
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| 361 | CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
|
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| 362 | }
|
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| 363 | }
|
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| 364 |
|
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| 365 | /** Initialize USB TLL port connections.
|
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| 366 | *
|
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| 367 | * Different modes are on page 3312 of the Manual Figure 22-34.
|
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| 368 | * Select mode than can operate in FS/LS.
|
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| 369 | */
|
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[b7fd2a0] | 370 | errno_t amdm37x_usb_tll_init(amdm37x_t *device)
|
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[7a6d91b] | 371 | {
|
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| 372 | /* Check access */
|
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| 373 | if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) {
|
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| 374 | ddf_msg(LVL_ERROR, "USB TLL is not accessible");
|
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| 375 | return EIO;
|
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| 376 | }
|
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| 377 |
|
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| 378 | /* Reset USB TLL */
|
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| 379 | pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
|
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| 380 | ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
|
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[18b6a88] | 381 | while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG))
|
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| 382 | ;
|
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[7a6d91b] | 383 | ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
|
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| 384 |
|
---|
| 385 | /* Setup idle mode (smart idle) */
|
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| 386 | pio_change_32(&device->tll->sysconfig,
|
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| 387 | TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
|
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| 388 | TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
|
---|
| 389 |
|
---|
| 390 | /* Smart idle for UHH */
|
---|
| 391 | pio_change_32(&device->uhh->sysconfig,
|
---|
| 392 | UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
|
---|
| 393 | UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
|
---|
| 394 |
|
---|
[7c3fb9b] | 395 | /*
|
---|
| 396 | * Set all ports to go through TLL(UTMI)
|
---|
| 397 | * Direct connection can only work in HS mode
|
---|
| 398 | */
|
---|
[7a6d91b] | 399 | pio_set_32(&device->uhh->hostconfig,
|
---|
| 400 | UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
|
---|
| 401 | UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
|
---|
| 402 | UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
|
---|
| 403 |
|
---|
| 404 | /* What is this? */
|
---|
| 405 | pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
|
---|
| 406 |
|
---|
| 407 | for (unsigned i = 0; i < 3; ++i) {
|
---|
[7c3fb9b] | 408 | /*
|
---|
| 409 | * Serial mode is the only one capable of FS/LS operation.
|
---|
[7a6d91b] | 410 | * Select FS/LS mode, no idea what the difference is
|
---|
| 411 | * one of bidirectional modes might be good choice
|
---|
[7c3fb9b] | 412 | * 2 = 3pin bidi phy.
|
---|
| 413 | */
|
---|
[7a6d91b] | 414 | pio_change_32(&device->tll->channel_conf[i],
|
---|
| 415 | TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
|
---|
| 416 | TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
|
---|
| 417 | TLL_CHANNEL_CONF_CHANMODE_MASK |
|
---|
| 418 | TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
|
---|
| 419 | }
|
---|
| 420 | return EOK;
|
---|
| 421 | }
|
---|
[4122410] | 422 |
|
---|
| 423 | /**
|
---|
| 424 | * @}
|
---|
| 425 | */
|
---|