source: mainline/uspace/drv/platform/amdm37x/amdm37x.c@ 84239b1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 84239b1 was 84239b1, checked in by Jiri Svoboda <jiri@…>, 7 years ago

And there was much fixing.
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File size: 15.1 KB
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[7a6d91b]1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
[0f2a9be]30 * @defgroup amdm37x TI AM/DM37x platform driver.
[7a6d91b]31 * @brief HelenOS TI AM/DM37x platform driver.
32 * @{
33 */
34
35/** @file
36 */
37
38#include "amdm37x.h"
39
40#include <assert.h>
41#include <ddi.h>
42#include <ddf/log.h>
43#include <errno.h>
44#include <stdio.h>
45
[aa537a5a]46static void
47log(const volatile void *place, uint64_t val, volatile void *base, size_t size,
48 void *data, bool write)
[7a6d91b]49{
[aa537a5a]50 printf("PIO %s: %p(%p) %#"PRIx64"\n", write ? "WRITE" : "READ",
[7a6d91b]51 (place - base) + data, place, val);
52}
53
54
[b7fd2a0]55errno_t amdm37x_init(amdm37x_t *device, bool trace)
[7a6d91b]56{
57 assert(device);
[b7fd2a0]58 errno_t ret = EOK;
[7a6d91b]59
60 ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
61 (void**)&device->cm.usbhost);
62 if (ret != EOK)
63 return ret;
64
65 ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
66 (void**)&device->cm.core);
67 if (ret != EOK)
68 return ret;
69
70 ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS,
71 CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks);
72 if (ret != EOK)
73 return ret;
74
75 ret = pio_enable((void*)MPU_CM_BASE_ADDRESS,
76 MPU_CM_SIZE, (void**)&device->cm.mpu);
77 if (ret != EOK)
78 return ret;
79
80 ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS,
81 IVA2_CM_SIZE, (void**)&device->cm.iva2);
82 if (ret != EOK)
83 return ret;
84
85 ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS,
86 CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks);
87 if (ret != EOK)
88 return ret;
89
90 ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS,
91 GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global);
92 if (ret != EOK)
93 return ret;
94
95 ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS,
96 AMDM37x_USBTLL_SIZE, (void**)&device->tll);
97 if (ret != EOK)
98 return ret;
99
100 ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS,
101 AMDM37x_UHH_SIZE, (void**)&device->uhh);
102 if (ret != EOK)
103 return ret;
104
105 if (trace) {
106 pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS);
107 pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS);
108 pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS);
109 pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS);
110 pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS);
111 pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS);
112 pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS);
113 pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS);
114 pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS);
115 }
116 return EOK;
117}
118
119
120/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
121 * @param device Register map.
122 *
123 * The idea is to get all DPLLs running and make hw control their power mode,
124 * based on the module requirements (module ICLKs and FCLKs).
125 */
126void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device)
127{
128 assert(device);
129 /* Get SYS_CLK value, it is used as reference clock by all DPLLs,
130 * NFI who sets this or why it is set to specific value. */
131 const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel)
132 & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
133 const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
134 const unsigned base_freq = sys_clk_freq_kHz(osc_clk)
135 / GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
136 ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
137 base_freq / 1000, base_freq % 1000);
138
139
140 /* DPLL1 provides MPU(CPU) clock.
141 * It uses SYS_CLK as reference clock and core clock (DPLL3) as
142 * high frequency bypass (MPU then runs on L3 interconnect freq).
143 * It should be setup by fw or u-boot.*/
144 mpu_cm_regs_t *mpu = device->cm.mpu;
145
146 /* Current MPU frequency. */
147 if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
148 if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
149 /* DPLL active and locked */
150 const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
151 const unsigned multiplier =
152 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK)
153 >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
154 const unsigned divisor =
155 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK)
156 >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT;
157 const unsigned divisor2 =
158 (pio_read_32(&mpu->clksel2_pll)
159 & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
160 if (multiplier && divisor && divisor2) {
161 /** See AMDM37x TRM p. 300 for the formula */
162 const unsigned freq =
163 ((base_freq * multiplier) / (divisor + 1))
164 / divisor2;
165 ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
166 freq / 1000, freq % 1000);
167 } else {
168 ddf_msg(LVL_WARN, "Frequency divisor and/or "
169 "multiplier value invalid: %d %d %d",
170 multiplier, divisor, divisor2);
171 }
172 } else {
173 /* DPLL in LP bypass mode */
174 const unsigned divisor =
175 MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
176 pio_read_32(&mpu->clksel1_pll));
177 ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
178 " CORE CLK / %d MHz", divisor);
179 }
180 } else {
181 ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
182 }
183 // TODO: Enable this (automatic MPU downclocking):
184#if 0
185 /* Enable low power bypass mode, this will take effect the next lock or
186 * relock sequence. */
187 //TODO: We might need to force re-lock after enabling this
188 pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
189 /* Enable automatic relocking */
190 pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
191#endif
192
193 /* DPLL2 provides IVA(video acceleration) clock.
194 * It uses SYS_CLK as reference clokc and core clock (DPLL3) as
195 * high frequency bypass (IVA runs on L3 freq).
196 */
197 // TODO: We can probably turn this off entirely. IVA is left unused.
198 /* Enable low power bypass mode, this will take effect the next lock or
199 * relock sequence. */
200 //TODO: We might need to force re-lock after enabling this
201 pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
202 /* Enable automatic relocking */
203 pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
204
205 /* DPLL3 provides tons of clocks:
206 * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
207 * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
208 * bypass. It should be setup by fw or u-boot as it controls critical
209 * interconnects.
210 */
211 if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
212 /* DPLL active and locked */
213 const uint32_t reg =
214 pio_read_32(&device->cm.clocks->clksel1_pll);
215 const unsigned multiplier =
216 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
217 const unsigned divisor =
218 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
219 const unsigned divisor2 =
220 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
221 if (multiplier && divisor && divisor2) {
222 /** See AMDM37x TRM p. 300 for the formula */
223 const unsigned freq =
224 ((base_freq * multiplier) / (divisor + 1)) / divisor2;
225 ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
226 freq / 1000, freq % 1000);
227 const unsigned l3_div =
228 pio_read_32(&device->cm.core->clksel)
229 & CORE_CM_CLKSEL_CLKSEL_L3_MASK;
230 if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
231 l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
232 ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
233 (freq / l3_div) / 1000,
234 (freq / l3_div) % 1000);
235 } else {
236 ddf_msg(LVL_WARN,"L3 interface clock divisor is"
237 " invalid: %d", l3_div);
238 }
239 } else {
240 ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
241 "multiplier value invalid: %d %d %d",
242 multiplier, divisor, divisor2);
243 }
244 } else {
245 ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
246 " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
247 }
248
249 /* Set DPLL3 to automatic to save power */
250 pio_change_32(&device->cm.clocks->autoidle_pll,
251 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
252 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
253
254 /* DPLL4 provides peripheral domain clocks:
255 * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
256 * It uses SYS_CLK as reference clock and low frequency bypass.
257 * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
258 * we can probably turn this off entirely (DSS is still non-functional).
259 */
260 /* Set DPLL4 to automatic to save power */
261 pio_change_32(&device->cm.clocks->autoidle_pll,
262 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
263 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
264
265 /* DPLL5 provide peripheral domain clocks: 120M_FCLK.
266 * It uses SYS_CLK as reference clock and low frequency bypass.
267 * 120M clock is used by HS USB and USB TLL.
268 */
269 // TODO setup DPLL5
270 if ((pio_read_32(&device->cm.clocks->clken2_pll)
271 & CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK)
272 != CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
273 /* Compute divisors and multiplier
274 * See AMDM37x TRM p. 300 for the formula */
[0f2c80a]275 // TODO: base_freq does not have to be rounded to Mhz
276 // (that's why I used KHz as unit).
277 const unsigned mult = 120;
278 const unsigned div = (base_freq / 1000) - 1;
[7a6d91b]279 const unsigned div2 = 1;
[0f2c80a]280 if ( ((base_freq % 1000) != 0) || (div > 127)) {
281 ddf_msg(LVL_ERROR, "Rounding error, or divisor to big "
282 "freq: %d, div: %d", base_freq, div);
283 return;
[84239b1]284 }
[0f2c80a]285 assert(div <= 127);
[7a6d91b]286
287 /* Set multiplier */
288 pio_change_32(&device->cm.clocks->clksel4_pll,
289 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
290 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
291
292 /* Set DPLL divisor */
293 pio_change_32(&device->cm.clocks->clksel4_pll,
294 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
295 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
296
297 /* Set output clock divisor */
298 pio_change_32(&device->cm.clocks->clksel5_pll,
299 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
300 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
301
302 /* Start DPLL5 */
303 pio_change_32(&device->cm.clocks->clken2_pll,
304 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
305 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
306
307 }
308 /* Set DPLL5 to automatic to save power */
309 pio_change_32(&device->cm.clocks->autoidle2_pll,
310 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
311 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
312}
313
314/** Enable/disable function and interface clocks for USBTLL and USBHOST.
315 * @param device Register map.
316 * @param on True to switch clocks on.
317 */
318void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled)
319{
320 if (enabled) {
321 /* Enable interface and function clock for USB TLL */
322 pio_set_32(&device->cm.core->fclken3,
323 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
324 pio_set_32(&device->cm.core->iclken3,
325 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
326
327 /* Enable interface and function clock for USB hosts */
328 pio_set_32(&device->cm.usbhost->fclken,
329 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
330 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
331 pio_set_32(&device->cm.usbhost->iclken,
332 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
333#if 0
334 printf("DPLL5 (and everything else) should be on: %"
335 PRIx32" %"PRIx32".\n",
336 pio_read_32(&device->cm.clocks->idlest_ckgen),
337 pio_read_32(&device->cm.clocks->idlest2_ckgen));
338#endif
339 } else {
340 /* Disable interface and function clock for USB hosts */
341 pio_clear_32(&device->cm.usbhost->iclken,
342 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
343 pio_clear_32(&device->cm.usbhost->fclken,
344 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
345 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
346
347 /* Disable interface and function clock for USB TLL */
348 pio_clear_32(&device->cm.core->iclken3,
349 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
350 pio_clear_32(&device->cm.core->fclken3,
351 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
352 }
353}
354
355/** Initialize USB TLL port connections.
356 *
357 * Different modes are on page 3312 of the Manual Figure 22-34.
358 * Select mode than can operate in FS/LS.
359 */
[b7fd2a0]360errno_t amdm37x_usb_tll_init(amdm37x_t *device)
[7a6d91b]361{
362 /* Check access */
363 if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) {
364 ddf_msg(LVL_ERROR, "USB TLL is not accessible");
365 return EIO;
366 }
367
368 /* Reset USB TLL */
369 pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
370 ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
371 while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG));
372 ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
373
374 /* Setup idle mode (smart idle) */
375 pio_change_32(&device->tll->sysconfig,
376 TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
377 TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
378
379 /* Smart idle for UHH */
380 pio_change_32(&device->uhh->sysconfig,
381 UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
382 UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
383
384 /* Set all ports to go through TLL(UTMI)
385 * Direct connection can only work in HS mode */
386 pio_set_32(&device->uhh->hostconfig,
387 UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
388 UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
389 UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
390
391 /* What is this? */
392 pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
393
394 for (unsigned i = 0; i < 3; ++i) {
395 /* Serial mode is the only one capable of FS/LS operation.
396 * Select FS/LS mode, no idea what the difference is
397 * one of bidirectional modes might be good choice
398 * 2 = 3pin bidi phy. */
399 pio_change_32(&device->tll->channel_conf[i],
400 TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
401 TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
402 TLL_CHANNEL_CONF_CHANMODE_MASK |
403 TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
404 }
405 return EOK;
406}
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