source: mainline/uspace/drv/pciintel/pci.c@ dc75234

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since dc75234 was dc75234, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Remove possible endless cycle
  • Property mode set to 100644
File size: 16.4 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <stdio.h>
41#include <errno.h>
42#include <bool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <devman.h>
51#include <ipc/devman.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ipc/ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ddi.h>
60#include <libarch/ddi.h>
61#include <pci_dev_iface.h>
62
63#include "pci.h"
64
65#define NAME "pciintel"
66
67#define CONF_ADDR(bus, dev, fn, reg) \
68 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
69
70/** Obtain PCI function soft-state from DDF function node */
71#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
72
73/** Obtain PCI bus soft-state from DDF device node */
74#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
75
76/** Obtain PCI bus soft-state from function soft-state */
77#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
78
79static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
80{
81 pci_fun_t *fun = PCI_FUN(fnode);
82
83 if (fun == NULL)
84 return NULL;
85 return &fun->hw_resources;
86}
87
88static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
89{
90 /* This is an old ugly way, copied from ne2000 driver */
91 assert(fnode);
92 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data;
93
94 sysarg_t apic;
95 sysarg_t i8259;
96
97 int irc_phone = -1;
98 int irc_service = 0;
99
100 if ((sysinfo_get_value("apic", &apic) == EOK) && (apic)) {
101 irc_service = SERVICE_APIC;
102 } else if ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259)) {
103 irc_service = SERVICE_I8259;
104 }
105
106 if (irc_service == 0)
107 return false;
108
109 irc_phone = service_connect_blocking(irc_service, 0, 0);
110 if (irc_phone < 0)
111 return false;
112
113 size_t i;
114 for (i = 0; i < dev_data->hw_resources.count; i++) {
115 if (dev_data->hw_resources.resources[i].type == INTERRUPT) {
116 int irq = dev_data->hw_resources.resources[i].res.interrupt.irq;
117 int rc = async_req_1_0(irc_phone, IRC_ENABLE_INTERRUPT, irq);
118 if (rc != EOK) {
119 async_hangup(irc_phone);
120 return false;
121 }
122 }
123 }
124
125 async_hangup(irc_phone);
126 return true;
127}
128
129static int pci_config_space_write_16(ddf_fun_t *fun, uint32_t address, uint16_t data)
130{
131 if (address > 254)
132 return EINVAL;
133 pci_conf_write_16(PCI_FUN(fun), address, data);
134 return EOK;
135}
136
137
138static hw_res_ops_t pciintel_hw_res_ops = {
139 &pciintel_get_resources,
140 &pciintel_enable_interrupt
141};
142
143static pci_dev_iface_t pci_dev_ops = {
144 .config_space_read_8 = NULL,
145 .config_space_read_16 = NULL,
146 .config_space_read_32 = NULL,
147 .config_space_write_8 = NULL,
148 .config_space_write_16 = &pci_config_space_write_16,
149 .config_space_write_32 = NULL
150};
151
152static ddf_dev_ops_t pci_fun_ops = {
153 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
154 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
155};
156
157static int pci_add_device(ddf_dev_t *);
158
159/** PCI bus driver standard operations */
160static driver_ops_t pci_ops = {
161 .add_device = &pci_add_device
162};
163
164/** PCI bus driver structure */
165static driver_t pci_driver = {
166 .name = NAME,
167 .driver_ops = &pci_ops
168};
169
170static pci_bus_t *pci_bus_new(void)
171{
172 pci_bus_t *bus;
173
174 bus = (pci_bus_t *) calloc(1, sizeof(pci_bus_t));
175 if (bus == NULL)
176 return NULL;
177
178 fibril_mutex_initialize(&bus->conf_mutex);
179 return bus;
180}
181
182static void pci_bus_delete(pci_bus_t *bus)
183{
184 assert(bus != NULL);
185 free(bus);
186}
187
188static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
189{
190 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
191
192 fibril_mutex_lock(&bus->conf_mutex);
193
194 uint32_t conf_addr;
195 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
196 void *addr = bus->conf_data_port + (reg & 3);
197
198 pio_write_32(bus->conf_addr_port, conf_addr);
199
200 switch (len) {
201 case 1:
202 buf[0] = pio_read_8(addr);
203 break;
204 case 2:
205 ((uint16_t *) buf)[0] = pio_read_16(addr);
206 break;
207 case 4:
208 ((uint32_t *) buf)[0] = pio_read_32(addr);
209 break;
210 }
211
212 fibril_mutex_unlock(&bus->conf_mutex);
213}
214
215static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
216{
217 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
218
219 fibril_mutex_lock(&bus->conf_mutex);
220
221 uint32_t conf_addr;
222 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
223 void *addr = bus->conf_data_port + (reg & 3);
224
225 pio_write_32(bus->conf_addr_port, conf_addr);
226
227 switch (len) {
228 case 1:
229 pio_write_8(addr, buf[0]);
230 break;
231 case 2:
232 pio_write_16(addr, ((uint16_t *) buf)[0]);
233 break;
234 case 4:
235 pio_write_32(addr, ((uint32_t *) buf)[0]);
236 break;
237 }
238
239 fibril_mutex_unlock(&bus->conf_mutex);
240}
241
242uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
243{
244 uint8_t res;
245 pci_conf_read(fun, reg, &res, 1);
246 return res;
247}
248
249uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
250{
251 uint16_t res;
252 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
253 return res;
254}
255
256uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
257{
258 uint32_t res;
259 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
260 return res;
261}
262
263void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
264{
265 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
266}
267
268void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
269{
270 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
271}
272
273void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
274{
275 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
276}
277
278void pci_fun_create_match_ids(pci_fun_t *fun)
279{
280 char *match_id_str;
281 int rc;
282
283 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
284 fun->vendor_id, fun->device_id);
285
286 if (match_id_str == NULL) {
287 printf(NAME ": out of memory creating match ID.\n");
288 return;
289 }
290
291 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
292 if (rc != EOK) {
293 printf(NAME ": error adding match ID: %s\n",
294 str_error(rc));
295 }
296
297 /* TODO add more ids (with subsys ids, using class id etc.) */
298}
299
300void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
301 bool io)
302{
303 hw_resource_list_t *hw_res_list = &fun->hw_resources;
304 hw_resource_t *hw_resources = hw_res_list->resources;
305 size_t count = hw_res_list->count;
306
307 assert(hw_resources != NULL);
308 assert(count < PCI_MAX_HW_RES);
309
310 if (io) {
311 hw_resources[count].type = IO_RANGE;
312 hw_resources[count].res.io_range.address = range_addr;
313 hw_resources[count].res.io_range.size = range_size;
314 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
315 } else {
316 hw_resources[count].type = MEM_RANGE;
317 hw_resources[count].res.mem_range.address = range_addr;
318 hw_resources[count].res.mem_range.size = range_size;
319 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
320 }
321
322 hw_res_list->count++;
323}
324
325/** Read the base address register (BAR) of the device and if it contains valid
326 * address add it to the devices hw resource list.
327 *
328 * @param fun PCI function
329 * @param addr The address of the BAR in the PCI configuration address space of
330 * the device
331 * @return The addr the address of the BAR which should be read next
332 */
333int pci_read_bar(pci_fun_t *fun, int addr)
334{
335 /* Value of the BAR */
336 uint32_t val, mask;
337 /* IO space address */
338 bool io;
339 /* 64-bit wide address */
340 bool addrw64;
341
342 /* Size of the io or memory range specified by the BAR */
343 size_t range_size;
344 /* Beginning of the io or memory range specified by the BAR */
345 uint64_t range_addr;
346
347 /* Get the value of the BAR. */
348 val = pci_conf_read_32(fun, addr);
349
350#define IO_MASK (~0x3)
351#define MEM_MASK (~0xf)
352
353 io = (bool) (val & 1);
354 if (io) {
355 addrw64 = false;
356 mask = IO_MASK;
357 } else {
358 mask = MEM_MASK;
359 switch ((val >> 1) & 3) {
360 case 0:
361 addrw64 = false;
362 break;
363 case 2:
364 addrw64 = true;
365 break;
366 default:
367 /* reserved, go to the next BAR */
368 return addr + 4;
369 }
370 }
371
372 /* Get the address mask. */
373 pci_conf_write_32(fun, addr, 0xffffffff);
374 mask &= pci_conf_read_32(fun, addr);
375
376 /* Restore the original value. */
377 pci_conf_write_32(fun, addr, val);
378 val = pci_conf_read_32(fun, addr);
379
380 range_size = pci_bar_mask_to_size(mask);
381
382 if (addrw64) {
383 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
384 (val & 0xfffffff0);
385 } else {
386 range_addr = (val & 0xfffffff0);
387 }
388
389 if (range_addr != 0) {
390 printf(NAME ": function %s : ", fun->fnode->name);
391 printf("address = %" PRIx64, range_addr);
392 printf(", size = %x\n", (unsigned int) range_size);
393 }
394
395 pci_add_range(fun, range_addr, range_size, io);
396
397 if (addrw64)
398 return addr + 8;
399
400 return addr + 4;
401}
402
403void pci_add_interrupt(pci_fun_t *fun, int irq)
404{
405 hw_resource_list_t *hw_res_list = &fun->hw_resources;
406 hw_resource_t *hw_resources = hw_res_list->resources;
407 size_t count = hw_res_list->count;
408
409 assert(NULL != hw_resources);
410 assert(count < PCI_MAX_HW_RES);
411
412 hw_resources[count].type = INTERRUPT;
413 hw_resources[count].res.interrupt.irq = irq;
414
415 hw_res_list->count++;
416
417 printf(NAME ": function %s uses irq %x.\n", fun->fnode->name, irq);
418}
419
420void pci_read_interrupt(pci_fun_t *fun)
421{
422 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
423 if (irq != 0xff)
424 pci_add_interrupt(fun, irq);
425}
426
427/** Enumerate (recursively) and register the devices connected to a pci bus.
428 *
429 * @param bus Host-to-PCI bridge
430 * @param bus_num Bus number
431 */
432void pci_bus_scan(pci_bus_t *bus, int bus_num)
433{
434 ddf_fun_t *fnode;
435 pci_fun_t *fun;
436
437 int child_bus = 0;
438 int dnum, fnum;
439 bool multi;
440 uint8_t header_type;
441
442 fun = pci_fun_new(bus);
443
444 for (dnum = 0; dnum < 32; dnum++) {
445 multi = true;
446 for (fnum = 0; multi && fnum < 8; fnum++) {
447 pci_fun_init(fun, bus_num, dnum, fnum);
448 fun->vendor_id = pci_conf_read_16(fun,
449 PCI_VENDOR_ID);
450 fun->device_id = pci_conf_read_16(fun,
451 PCI_DEVICE_ID);
452 if (fun->vendor_id == 0xffff) {
453 /*
454 * The device is not present, go on scanning the
455 * bus.
456 */
457 if (fnum == 0)
458 break;
459 else
460 continue;
461 }
462
463 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
464 if (fnum == 0) {
465 /* Is the device multifunction? */
466 multi = header_type >> 7;
467 }
468 /* Clear the multifunction bit. */
469 header_type = header_type & 0x7F;
470
471 char *fun_name = pci_fun_create_name(fun);
472 if (fun_name == NULL) {
473 printf(NAME ": out of memory.\n");
474 return;
475 }
476
477 fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
478 if (fnode == NULL) {
479 printf(NAME ": error creating function.\n");
480 return;
481 }
482
483 free(fun_name);
484 fun->fnode = fnode;
485
486 pci_alloc_resource_list(fun);
487 pci_read_bars(fun);
488 pci_read_interrupt(fun);
489
490 fnode->ops = &pci_fun_ops;
491 fnode->driver_data = fun;
492
493 printf(NAME ": adding new function %s.\n",
494 fnode->name);
495
496 pci_fun_create_match_ids(fun);
497
498 if (ddf_fun_bind(fnode) != EOK) {
499 pci_clean_resource_list(fun);
500 clean_match_ids(&fnode->match_ids);
501 free((char *) fnode->name);
502 fnode->name = NULL;
503 continue;
504 }
505
506 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
507 header_type == PCI_HEADER_TYPE_CARDBUS) {
508 child_bus = pci_conf_read_8(fun,
509 PCI_BRIDGE_SEC_BUS_NUM);
510 printf(NAME ": device is pci-to-pci bridge, "
511 "secondary bus number = %d.\n", bus_num);
512 if (child_bus > bus_num)
513 pci_bus_scan(bus, child_bus);
514 }
515
516 fun = pci_fun_new(bus);
517 }
518 }
519
520 if (fun->vendor_id == 0xffff) {
521 /* Free the auxiliary function structure. */
522 pci_fun_delete(fun);
523 }
524}
525
526static int pci_add_device(ddf_dev_t *dnode)
527{
528 pci_bus_t *bus = NULL;
529 ddf_fun_t *ctl = NULL;
530 bool got_res = false;
531 int rc;
532
533 printf(NAME ": pci_add_device\n");
534 dnode->parent_phone = -1;
535
536 bus = pci_bus_new();
537 if (bus == NULL) {
538 printf(NAME ": pci_add_device allocation failed.\n");
539 rc = ENOMEM;
540 goto fail;
541 }
542 bus->dnode = dnode;
543 dnode->driver_data = bus;
544
545 dnode->parent_phone = devman_parent_device_connect(dnode->handle,
546 IPC_FLAG_BLOCKING);
547 if (dnode->parent_phone < 0) {
548 printf(NAME ": pci_add_device failed to connect to the "
549 "parent's driver.\n");
550 rc = dnode->parent_phone;
551 goto fail;
552 }
553
554 hw_resource_list_t hw_resources;
555
556 rc = hw_res_get_resource_list(dnode->parent_phone, &hw_resources);
557 if (rc != EOK) {
558 printf(NAME ": pci_add_device failed to get hw resources for "
559 "the device.\n");
560 goto fail;
561 }
562 got_res = true;
563
564 printf(NAME ": conf_addr = %" PRIx64 ".\n",
565 hw_resources.resources[0].res.io_range.address);
566
567 assert(hw_resources.count > 0);
568 assert(hw_resources.resources[0].type == IO_RANGE);
569 assert(hw_resources.resources[0].res.io_range.size == 8);
570
571 bus->conf_io_addr =
572 (uint32_t) hw_resources.resources[0].res.io_range.address;
573
574 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
575 &bus->conf_addr_port)) {
576 printf(NAME ": failed to enable configuration ports.\n");
577 rc = EADDRNOTAVAIL;
578 goto fail;
579 }
580 bus->conf_data_port = (char *) bus->conf_addr_port + 4;
581
582 /* Make the bus device more visible. It has no use yet. */
583 printf(NAME ": adding a 'ctl' function\n");
584
585 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
586 if (ctl == NULL) {
587 printf(NAME ": error creating control function.\n");
588 rc = ENOMEM;
589 goto fail;
590 }
591
592 rc = ddf_fun_bind(ctl);
593 if (rc != EOK) {
594 printf(NAME ": error binding control function.\n");
595 goto fail;
596 }
597
598 /* Enumerate functions. */
599 printf(NAME ": scanning the bus\n");
600 pci_bus_scan(bus, 0);
601
602 hw_res_clean_resource_list(&hw_resources);
603
604 return EOK;
605
606fail:
607 if (bus != NULL)
608 pci_bus_delete(bus);
609 if (dnode->parent_phone >= 0)
610 async_hangup(dnode->parent_phone);
611 if (got_res)
612 hw_res_clean_resource_list(&hw_resources);
613 if (ctl != NULL)
614 ddf_fun_destroy(ctl);
615
616 return rc;
617}
618
619static void pciintel_init(void)
620{
621 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
622 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
623}
624
625pci_fun_t *pci_fun_new(pci_bus_t *bus)
626{
627 pci_fun_t *fun;
628
629 fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
630 if (fun == NULL)
631 return NULL;
632
633 fun->busptr = bus;
634 return fun;
635}
636
637void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
638{
639 fun->bus = bus;
640 fun->dev = dev;
641 fun->fn = fn;
642}
643
644void pci_fun_delete(pci_fun_t *fun)
645{
646 assert(fun != NULL);
647 hw_res_clean_resource_list(&fun->hw_resources);
648 free(fun);
649}
650
651char *pci_fun_create_name(pci_fun_t *fun)
652{
653 char *name = NULL;
654
655 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
656 fun->fn);
657 return name;
658}
659
660bool pci_alloc_resource_list(pci_fun_t *fun)
661{
662 fun->hw_resources.resources =
663 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
664 return fun->hw_resources.resources != NULL;
665}
666
667void pci_clean_resource_list(pci_fun_t *fun)
668{
669 if (fun->hw_resources.resources != NULL) {
670 free(fun->hw_resources.resources);
671 fun->hw_resources.resources = NULL;
672 }
673}
674
675/** Read the base address registers (BARs) of the function and add the addresses
676 * to its HW resource list.
677 *
678 * @param fun PCI function
679 */
680void pci_read_bars(pci_fun_t *fun)
681{
682 /*
683 * Position of the BAR in the PCI configuration address space of the
684 * device.
685 */
686 int addr = PCI_BASE_ADDR_0;
687
688 while (addr <= PCI_BASE_ADDR_5)
689 addr = pci_read_bar(fun, addr);
690}
691
692size_t pci_bar_mask_to_size(uint32_t mask)
693{
694 size_t size = mask & ~(mask - 1);
695 return size;
696}
697
698int main(int argc, char *argv[])
699{
700 printf(NAME ": HelenOS pci bus driver (intel method 1).\n");
701 pciintel_init();
702 return ddf_driver_main(&pci_driver);
703}
704
705/**
706 * @}
707 */
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